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7 - 1 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz functional diagram features ? rf bandwidth: 25 - 6000 mhz ? maximum phase detector rate 100 mhz ? ultra low phase noise -110 dbc/hz in band typ. ? figure of merit (fom) -227 dbc/hz ? <180 fs rms jitter ? 24-bit step size, resolution 3 hz typ ? exact frequency mode ? built in digital self test ? 40 lead 6x6 mm smt package: 36 mm 2 typical applications ? cellular infrastructure ? microwave radio ? wimax, wifi ? communications te st eq uipment ? catv equipment ? dds replacement ? military ? tunable reference source for spurious- free performance plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 2 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz general description the HMC833LP6GE is a lo w no ise, wi de ba nd, fr actional-n ph ase-locked-loop (p ll) th at fe atures an in tegrated vo ltage controlled os cillator (v co) wi th a fu ndamental fre quency of 15 00 mh z - 30 00 mh z, an d an in tegrated vc o ou tput divider (divide by 1/ 2/4/6.../60/62) an d do ubler, th at tog ether al low th e hm c833lp6ge to ge nerate fre quencies fro m 25 mhz to 60 00 mh z. th e in tegrated ph ase de tector (p d) an d de lta-sigma mo dulator, ca pable of op erating at up to 100 mhz, permit wider loop-bandwidths with excellent spectral performance. the HMC833LP6GE fe atures in dustry le ading ph ase no ise an d sp urious pe rformance, ac ross al l fre quencies, th at enable it to mi nimize bl ocker ef fects, an d im prove re ceiver se nsitivity an d tr ansmitter sp ectral pu rity. th e su perior noise foor (< -1 70 db c/hz) ma kes th e hm c833lp6ge an id eal so urce fo r a va riety of ap plications - su ch as ; lo fo r rf mixers, a cl ock so urce fo r hi gh-frequency da ta-converters, or a tu nable re ference so urce fo r ul tra-low sp urious applications. additional fe atures of th e hm c833lp6ge in clude rf ou tput po wer co ntrol fro m 0 to 9 db (3 db st eps), ou tput mu te function, and a de lta-sigma mo dulator ex act fr equency mo de wh ich en ables us ers to ge nerate ou tput fre quencies with 0 hz frequency error. parameter condition min. typ. max. units rf output characteristics output frequency 25 6000 mhz vco frequency at pll input 1500 3000 mhz rf output frequency at f vco 1500 3000 mhz output power rf output power at f fundamental = 2000 mhz across all frequencies see figure 9 broadband ma tched in ternally [1] 1.5 3 4.5 dbm output power control range 3 9 db output power control step 0.75 3 db rf output power at f doubler = 3000 mhz across all frequencies see figure 9 broadband ma tched in ternally [1] -3.5 -2.5 -1 dbm rf output power at f doubler = 6000 mhz across all frequencies see figure 9 broadband ma tched in ternally [1] -11 -7 -5 dbm harmonics for fundamental mode fo mode at 2 ghz 2nd / 3rd / 4th -20/-29/-45 dbc fo/2 mode at 2ghz/2 = 1 ghz 2nd / 3rd / 4th -23/-15/-35 dbc fo/30 mode at 3 ghz/30 = 100 mhz 2nd / 3rd / 4th -25/-10/-33 dbc fo/62 mode at 1550 mhz/62 = 25 mhz 2nd / 3rd / 4th -17/-8/-21 dbc harmonics in doubler mode 2fo mode at 4 ghz ? / 3rd / 4th/5th -7/-23/-15/-40 -4/-15/-7/-28 dbc vco output divider vco rf divider range 1,2,4,6,8,...,62 1 62 electrical specifcations vppcp, vddls, vcc1, vcc2 = 5 v; rvdd, avdd, dvdd3v, vccpd, vcchf, vccps = 3.3 v min and max specifed across temp -40 c to 85 c [1] measured single-ended. additional 3 db possible with differential outputs. [2] measured with 100 external termination. see reference input stage section for more details. plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 3 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz parameter condition min. typ. max. units pll rf divider characteristics 19-bit n-divider range (integer) max = 2 19 - 1 16 524,287 19-bit n-divider range (fractional) fractional no minal di vide ra tio varies (-3 / +4) dynamically max 20 524,283 ref input characteristics max ref input frequency 350 mhz ref input voltage ac coupled [2] 1 2 3.3 vp-p ref input capacitance 5 pf 14-bit r-divider range 1 16,383 phase detector (pd) [3] pd frequency fractional mode b [4] dc 100 mhz pd frequency fractional mode a (and regis - ter 6 [17:16] = 11) dc 80 mhz pd frequency integer mode dc 125 mhz charge pump output current 0.02 2.54 ma charge pump gain step size 20 a pd/charge pump ssb phase noise 50 mhz ref, input referred 1 khz -143 dbc/hz 10 khz add 1 db for fractional -150 dbc/hz 100 khz add 3 db for fractional -153 dbc/hz logic inputs vsw 40 50 60 % dvdd logic outputs voh output high voltage dvdd v vol output low voltage 0 v output impedance 100 200 maximum load current 1.5 ma power supply voltages 3.3 v supplies avdd, vcchf, vccps, vccpd, rvdd,dvdd 3.0 3.3 3.5 v 5 v supplies vppcp, vddls, vcc1, vcc2 4.8 5 5.2 v power supply currents +5 v analog charge pump vppcp, vddcp 8 ma +5 v vco core and vco buffer fo/1 mode vcc2 105 ma fo/n mode vcc2 80 ma +5 v vco divider and rf/pll buffer fo/1 mode vcc1 25 ma fo/n mode vcc1 80 100 ma electrical specifcations (continued) [3] slew rate of greater or equal to 0.5 ns/v is recommended, see reference input stage section for more details. frequency is guaranteed across process voltage and temperature from -40 c to 85 c. [4] this maximum phase detector frequency can only be achieved if the minimum n value is respected. eg. in the case of fractional b mode, the maximum pfd rate = fvco/20 or 100 mhz, whichever is less. plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 4 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz electrical specifcations (continued) parameter condition min. typ. max. units +3.3 v avdd, vcchf, vccps, vccpd, rvdd, dvdd3v 52 ma power down - crystal off reg 01h=0, crystal not clocked 10 a power down - crystal on, 100 mhz reg 01h=0, crystal clocked 100 mhz 5 ma power on reset typical reset voltage on dvdd 700 mv min dvdd voltage for no reset 1.5 v power on reset delay 250 s vco open loop phase noise at fo @ 2 ghz 10 khz offset -86 dbc/hz 100 khz offset -116 dbc/hz 1 mhz offset -141 dbc/hz 10 mhz offset -162 dbc/hz 100 mhz offset -171 dbc/hz vco open loop phase noise at fo @ 2 ghz/2 = 1 ghz 10 khz offset -92 dbc/hz 100 khz offset -122 dbc/hz 1 mhz offset -147 dbc/hz 10 mhz offset -165 dbc/hz 100 mhz offset -165 dbc/hz vco open loop phase noise at fo @3 ghz/30 = 100 mhz 10 khz offset -112 dbc/hz 100 khz offset -142 dbc/hz 1 mhz offset -165 dbc/hz 10 mhz offset -168 dbc/hz 100 mhz offset -171 dbc/hz vco open loop phase noise at 2fo @ 4 ghz 10 khz offset -80 dbc/hz 100 khz offset -110 dbc/hz 1 mhz offset -135 dbc/hz 10 mhz offset -155 dbc/hz 100 mhz offset -162 dbc/hz vco open loop phase noise at 2fo @ 6 ghz 10 khz offset -75 dbc/hz 100 khz offset -105 dbc/hz 1 mhz offset -131 dbc/hz 10 mhz offset -152 dbc/hz 100 mhz offset -162 dbc/hz plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 5 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz parameter condition min. typ. max. units figure of merit floor integer mode normalized to 1 hz -230 dbc/hz floor fractional mode normalized to 1 hz -227 dbc/hz flicker (both modes) normalized to 1 hz -268 dbc/hz vco characteristics vco tuning sensitivity at 2800 mhz measured at 2.5 v 13.3 mhz/v vco tuning sensitivity at 2400 mhz measured at 2.5 v 13.8 mhz/v vco tuning sensitivity at 2000 mhz measured at 2.5 v 13.6 mhz/v vco tuning sensitivity at 1600 mhz measured at 2.5 v 12.1 mhz/v vco supply pushing measured at 2.5 v 2 mhz/v electrical specifcations (continued) plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 6 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz figure 1. typical closed loop integer phase noise [ loop filter con fguration ta ble ] figure 2. typical closed loop fractional phase noise [ loop filter con fguration ta ble ] figure 3. free running phase noise figure 4. free running vco phase noise vs. temperature figure 5. typical vco sensitivity at fo -220 -200 -180 -160 -140 -120 -100 -80 1 10 100 1000 10000 100000 fout 3800 mhz,lopp bw 74khz,rms jitter 108fsec fout 3800mhz,loop filter 90khz,rms jitter 87fsec fout 5600mhz,loop bw 74khz,rms jitter 188fsec fout 1600mhz,loop bw 74khz,rms jitter 127fsec fout 1600mhz,loop bw 90khz, rms jitter 97fsec fout 5600mhz,loop bw 90khz,rms jitter 118fsec offset(khz) phase noise(dbc/hz) -220 -200 -180 -160 -140 -120 -100 -80 1 10 100 1000 10000 100000 fout 3805 mhz,loop bw 74khz,rms jitter 123fsec fout 3805mhz,loop bw 90khz,rms jitter 104fsec fout 5605mhz,loop bw 74khz,rms jitter 202fsec fout 5605mhz,loop bw 90khz,rms jitter 128fsec fout 1605mhz, loop bw 74khz,rms jitter 130fsec fout 1605mhz, loop bw 90khz, rms jitter 123fsec offset (khz) phase noise (dbc) -180 -160 -140 -120 -100 -80 -60 -40 10 3 10 4 10 5 10 6 10 7 10 8 5536 mhz 4732 mhz 3885 mhz 3058 mhz phase noise (dbc/hz) offset (hz) -180 -170 -160 -150 -140 -130 -120 -110 -100 10 100 1000 10000 27c -40c 85c phase noise (dbc/hz) frequency (mhz) 100 mhz offset 1 mhz offset 100 khz offset 0 1 2 3 4 5 tune voltage after calibration (v) vco frequency(mhz) fmin fmax 1500 3000 0 10 20 30 40 50 60 012345 2817 mhz at 2.5v, tuning cap 15 2418 mhz at 2.5v, tuning cap 15 1996 mhz at 2.5v, tuning cap 15 1575 mhz at 2.5v, tuning cap 15 tuning voltage (v) kvco (mhz/v) typical performance characteristics figure 6. typical tuning voltage after calibration at fo plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 7 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz figure 7. integrated rms jitter [1] [1] rms jitter data is measured in fractional mode with 100 khz loop bandwidth using 50 mhz reference frequency from 1 khz to 20 mhz integration ba ndwidth. [2] the output power from frequency 25mhz to 3000mhz is using fundamental confguration with gain setting 01, output power from frequency 3000mhz to 6000mhz is using doubler confguration with gain setting 11 [3] measured from a 50 source with a 100 external resistor termination. see reference input stage section for more details. full fom performance up to maximum 3.3 vpp input voltage. figure 8. figure of merit figure 9. typical output power vs. temperature [2] figure 10. output power vs gain control setting (vco_reg02h[8]=1. see vco_reg 02h ) figure 11. reference input sensitivity, square wave, 50 [3] figure 12. reference input sensitivity sinusoidal wave, 50 [3] 50 100 150 200 250 300 10 100 1000 10000 -40c 27c 85c jitter (fs) output frequency (mhz) -240 -230 -220 -210 -200 10 2 10 3 10 4 10 5 10 6 normalized phase noise (dbc/hz) frequency offset (hz) fom floor fom 1/f noise typ fom vs offset -12 -10 -8 -6 -4 -2 0 2 0 1000 2000 3000 4000 5000 6000 27 c -40 c 85 c output power (dbm) output frequency (mhz) -234 -232 -230 -228 -226 -224 -222 -220 -15 -12 -9 -6 -3 0 3 14 mhz square wave 25 mhz square wave 50 mhz square wave 100 mhz square wave fom reference power (dbm) -235 -230 -225 -220 -215 -210 -205 -200 -20 -15 -10 -5 0 5 14 mhz sin 25 mhz sin 50 mhz sin 100 mhz sin reference power (dbm) fom (dbc/hz) -10 -5 0 5 10 0 1000 2000 3000 4000 5000 6000 gain setting 11 gain setting 10 gain setting 01 gain setting 00 output power (dbm) output frequency (mhz) plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 8 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz figure 13. integer boundary spur at 5900.8 mhz [4] figure 14. integer boundary spur at 3900.4 mhz [5] -180 -160 -140 -120 -100 -80 -60 -40 -20 0 1 10 100 1000 10000 100000 phase noise (dbc/hz) offset (khz) [4] fractional mode b, 50 mhz pd frequency, 74 khz loop filter bw [5] fractional mode in mode b, integer boundary at 3800 mhz [7] exact frequency mode, ref in = 100 mhz, pd = 50 mhz, output divider 1 selected, loop filter bandwidth = 100 khz, channel spacing = 100 khz [8] exact frequency mode, channel spacing = 100 khz, fractional mode b rf out = 2591 mhz, ref in = 100 mhz, pd frequency = 50 mhz, output divider 1 selected, loop filter bandwidth = 120 khz, [9] fractional mode b rf out = 2591 mhz, ref in = 100 mhz, pd frequency = 50 mhz, output divider 1 selected, loop filter bandwidth = 120 khz. -180 -160 -140 -120 -100 -80 -60 -40 -20 0 1 10 100 1000 10000 100000 phase noise (dbc/hz) offset (khz) -180 -160 -140 -120 -100 -80 -60 -40 -20 0 1 10 100 1000 10000 100000 phase noise (dbc/hz) offset (khz) figure 15. fractional-n exact frequency mode on performance at 2113.5 mhz [7] figure 16. fractional-n exact frequency mode on performance at 2591 mhz [8] figure 17. fractional-n exact frequency mode off performance at 2591 mhz [9] -180 -160 -140 -120 -100 -80 -60 1000 10000 100000 1000000 10000000 100000000 phase noise (dbc/hz) offset (khz) -180 -160 -140 -120 -100 -80 -60 1 10 100 1000 10000 100000 phase noise (dbc/hz) offset (khz) -180 -160 -140 -120 -100 -80 -60 -40 -20 0 0.1 1 10 100 1000 10000 100000 phase noise (dbc/hz) offset (khz) figure 18. worst spur, fixed 50 mhz reference, output freq. = 2000.1 mhz [10] plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 9 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz loop filter bw (khz) c1 (pf) c2 (nf) c3 (pf) c4 (pf) r2 (k) r3 (k) r4 (k) loop filter design 74 150 27 220 220 0.82 1 1 90 270 3.9 56 56 1.2 1 1 200 56 1.8 n/a n/a 2.2 0 0 loop filter confguration table figure 19. rf output return loss figure 20. worst spur, tunable reference, output frequency = 2000.1 mhz [10] [10] capability of hmc830lp6ge to generate low frequencies (as low as 25 mhz), enables the hmc830lp6ge to be used as a tunable reference source into the HMC833LP6GE, which maximizes spur performance of the HMC833LP6GE. please see HMC833LP6GE application information for more information. [11] the graph is generated by observing, and plotting, the magnitude of only the worst spur (largest magnitude), at any offset, at each output frequency, while using a fxed 50 mhz reference and a tunable reference tuned to 47.5 mhz. see HMC833LP6GE application in formation for more details. [12] phase noise performance of the HMC833LP6GE when used as a tunable reference source. HMC833LP6GE is operating at 6 ghz/30, 6 ghz/54 for the 100 mhz, 55.55 mhz curves respectively loop filter 56 pf//(2.2k ohm+1.8 nf) integer mode 100mhz wenzel oscillator with rdiv=2 50mhz comparison frequency. figure 21. low frequency performance [11] -170 -160 -150 -140 -130 -120 0.1 1 10 100 1000 10000 100000 carrier frequency = 25 mhz carrier frequency = 55.55 mhz carrier frequency = 100 mhz phase noise (dbc/hz) offset (khz) figure 22. low frequency performance [12] -120 -110 -100 -90 -80 -70 -60 -50 2ghz +1khz 2ghz +10khz 2ghz +100khz 2ghz +1000khz 2ghz +10000khz fixed 50 mhz reference tunable reference worst spur (dbc) output frequency -180 -160 -140 -120 -100 -80 -60 -40 -20 0 0.1 1 10 100 1000 10000 100000 phase noise (dbc/hz) offset (khz) -35 -30 -25 -20 -15 -10 -5 0 25 100 1000 10000 return loss (db) frequency (mhz) plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 10 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz pin descriptions pin number function description 1 avdd dc power supply for analog circuitry. 2, 5, 6, 8, 9, 11 - 14, 18 - 22, 24, 26, 29, 34, 37, 38 n/c the pins are not connected internally; however, all data shown herein was measured with these pins connected to rf/dc ground externally. 3 vppcp power supply for charge pump analog section 4 cp charge pump output 7 vddls power supply for the charge pump digital section 10 rvdd reference supply 15 xrefp reference oscillator input 16 dvdd3v dc power supply for digital (cmos) circuitry 17 cen chip enable. connect to logic high for normal operation. 23 vtune vco varactor. tuning port input. 25 vcc2 vco analog supply 2 27 vcc1 vco analog supply 1 28 rf_out rf output 30 sen pll serial port enable (cmos) logic input 31 sdi pll serial port data (cmos) logic input 32 sck pll serial port clock (cmos) logic input 33 ld_sdo lock detect, or serial data, or general purpose (cmos) logic output (gpo) 35 vcchf dc power supply for analog circuitry 36 vccps dc power supply for analog prescaler 39 vccpd dc power supply for phase detector 40 bias external bypass decoupling for precision bias circuits. note: 1.920v 20mv reference voltage (bias) is generated internally and cannot drive an external load. must be measured with 10g meter such as agilent 34410a, normal 10m dvm will read erroneously. plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 11 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz outline drawing notes: 1. package body material: low stress injection molded plastic silica and silicon impregnated. 2. lead and ground paddle material: copper alloy. 3. lead and ground paddle plating: 100% matte tin. 4. dimensions are in inches [millimeters]. 5. lead spacing tolerance is non-cumulative. 6. pad burr length shall be 0.15mm max. pad burr height shall be 0.25mm max. 7. package warp shall not exceed 0.05mm. 8. all ground leads and ground paddle must be soldered to pcb rf ground. 9. refer to hittite application note for suggested pcb land pattern. absolute maximum ratings avdd, rvdd, dvdd3v, vccpd, vcchf, vcc ps -0.3v to +3.6v vppcp, vddls, vcc1,vcc2 -0.3v to +5.5v operating te mperature -40 c to +85c storage temperature -65 c to 150c maximum junction temperature 150 c thermal resistance (r th ) (junction to ground paddle) 9 c/w refow soldering peak temperature 260c time at peak temperature 40 sec esd sensitivity (hbm) class 1b stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter condition min. typ. max. units. temperature junction temperature 125 c ambient temperature -40 85 c supply voltage avdd, rvdd, dvdd3v, vccpd, vcchf, vccps 3.0 3.3 3.5 v vppcp 4.8 5.0 5.2 v recommended operating conditions plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 12 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz part number package body material lead finish msl rating package marking [1] HMC833LP6GE rohs-compliant low stress injection molded plastic 100% matte sn msl1 h833 xxxx [1] 4-digit lot number xxxx package information evaluation pcb schematic the circuit bo ard us ed in th e ap plication sh ould us e rf ci rcuit de sign te chniques. si gnal li nes sh ould ha ve 50 ohm impedance wh ile th e pa ckage gr ound le ads an d ex posed pa ddle sh ould be co nnected di rectly to th e ground plane si milar to th at sh own. a su fficient nu mber of vi a ho les sh ould be us ed to co nnect th e to p an d bottom ground planes. the evaluation circuit board shown is available from hittite upon request. to view this evaluation pc b sc hematic please visit www.hittite.com and choose HMC833LP6GE from the search by part number pull down menu to view the product splash page. evaluation pcb item contents part number evaluation kit HMC833LP6GE evaluation pcb usb interface board 6 usb a male to usb b female cable cd rom (contains user manual, evaluation pcb schematic, evaluation software, hittite pll design software) ekit01-HMC833LP6GE evaluation order information plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 13 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz HMC833LP6GE application information large bandwidth (2 5 mh z to 60 00 mh z), in dustry le ading ph ase no ise an d sp urious pe rformance, ex cellent no ise fo or (<-170 dbc/hz), co upled wi th a hi gh le vel of in tegration ma ke th e hm c833lp6ge id eal fo r a va riety of ap plications; as an rf or if st age lo , a cl ock so urce fo r hi gh-frequency da ta-converters, or a tu nable re ference so urce fo r ex tremely low spurious applications (< -100 dbc/hz spurs). figure 23. HMC833LP6GE in a typical transmit chain figure 24. HMC833LP6GE in a typical receive chain figure 25. hmc830lp6ge used as a tunable reference for HMC833LP6GE using the hm c833lp6ge wi th a tu nable re ference as sh own in figure 25 , it is possible to dr astically im prove sp urious emissions pe rformance ac ross al l fr equencies. ex ample sho wn in figure 20 graph shows th at it is po ssible to ha ve spurious emissions < -1 00 db c/hz ac ross al l fre quencies. fo r mo re in formation ab out sp urious em issions, ho w th ey are related to th e re ference fre quency, an d ho w to tu ne th e re ference fre quency fo r op timal sp urious pe rformance please s ee t he fractional ope ration an d sp urious section of this da ta sh eet. no te th at at ve ry lo w ou tput fre quencies < 100 mhz, ha rmonics in crease du e to sm all in ternal ac co upling. ap plications wh ich ar e se nsitive to ha rmonics ma y require external low pass fltering. plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 14 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz output gain setting for optimal power flatness the output of th e hm c833lp6ge is ma tched to 50 ac ross al l ou tput fre quencies fro m 25 mh z to 60 00 mh z. as a result of th e wi deband 50 ma tch, th e ou tput po wer of th e hm c833lp6ge de creases wi th in creasing ou tput frequency, as sh own in figure 9 . if required, it is po ssible to ad just th e ou tput st age ga in se tting of th e hm c833lp6ge ( vco_reg 0 2h b iases [7:6]) at various op erating fre quencies in or der to ac hieve a mo re co nstant ou tput po wer le vel across the frequency operating range of the HMC833LP6GE. an example is shown in figure 26 . figure 26. -20 -15 -10 -5 0 5 0 1000 2000 3000 4000 5000 6000 output power (dbm) output frequency (mhz) gain = 0 db gain = 9 db gain = 6 db divider output stage gain = 3 db (vco_reg02h[8] = 1) reducing the output power variation of HMC833LP6GE across frequency by adjusting output stage gain control. if a higher ou tput po wer th an th at sh own in figure 26 is required, it is po ssible to fo llow th e hm c833lp6ge ou tput stage with a si mple am plifer su ch as h m c 311sc70 e in order to ac hieve a co nstant an d hi gh ou tput po wer le vel across the entire operating range of the HMC833LP6GE. plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 15 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz 1.0 theory of operation HMC833LP6GE is targeted for ultra low phase noise applications and has been designed with very low noise reference path, phase detector and charge pump. the HMC833LP6GE consists of the following functional blocks: 1. reference path input buffers and r divider 2. vco path input buffer and multi-modulus n divider 3. ? fractional modulator 4. phase detector 5. charge pump 6. serial port with read write capability 7. general purpose output (gpo) port 8. power on reset circuit 9. vco subsystem 10. built-in self test features 1.1 vco subsystem the HMC833LP6GE contains a vco subsystem that can be confgured to operate in: ? fundamental frequency (fo) mode (1500 mhz to 3000 mhz). ? divide by n (fo/n), where n = 1,2,4,6,8...58,60,62 mode (25 mhz to 1500 mhz). ? doubler (2fo) mode (3000 mhz to 6000 mhz). all modes ar e vc o re gister pr ogrammable as sh own in figure 27 . one loop fl ter de sign ca n be us ed fo r the entire frequency of operation of the HMC833LP6GE. figure 27. pll and vco subsystems plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 16 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz 1.2 vco calibration 1.2.1 vco auto-calibration (autocal) HMC833LP6GE us es a st ep tu ned ty pe vc o. a si mplifed st ep tu ned vc o is sh own in figure 28 . a step tuned vco is a vc o wi th a di gitally se lectable ca pacitor ba nk al lowing th e no minal ce nter fre quency of th e vco to be ad justed or s tepped by sw itching in /out vc o ta nk ca pacitors. a mo re de tailed vi ew of a ty pical vco subsystem co nfguration is sh own in figure 29 . a step tuned vc o al lows th e us er to ce nter th e vc o on the required ou tput fre quency wh ile ke eping th e va ractor tu ning vo ltage op timized ne ar th e mi d-voltage tuning point of th e hm c833lp6ges ch arge pu mp. th is en ables th e pl l ch arge pu mp to tu ne th e vc o over the full range of operation with both a low tuning voltage and a low tuning sensitivity (kvco). the vco sw itches ar e no rmally co ntrolled au tomatically by th e hm c833lp6ge us ing th e auto-calibration fe ature. th e au to-calibration fe ature is im plemented in th e in ternal st ate ma chine. it manages the se lection of th e vc o su b-band (c apacitor se lection) wh en a ne w fre quency is pr ogrammed. the vco sw itches ma y al so be co ntrolled di rectly vi a re gister reg 05h for testing or fo r ot her sp ecial purpose operation. other control bits specifc to the vco are also sent via reg 05h . figure 28. simplifed step tuned vco figure 29. HMC833LP6GE pll and vco subsystems to use a step tu ned vc o in a cl osed lo op, th e vc o mu st be ca librated su ch th at th e hm c833lp6ge knows which sw itch po sition on th e vc o is op timum fo r th e de sired ou tput fre quency. th e hm c833lp6ge supports auto-calibration (a utocal) of th e st ep tu ned vc o. th e au tocal fx es th e vc o tu ning vo ltage at the optimum mi d-point of th e ch arge pu mp ou tput, th en me asures th e fre e ru nning vc o fre quency while searching fo r th e se tting wh ich re sults in th e fre e ru nning ou tput fre quency th at is cl osest to th e desired phase lo cked fre quency. th is pr ocedure re sults in a ph ase lo cked os cillator th at lo cks ov er plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 17 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz a very narrow vo ltage ra nge on th e va ractor. a ty pical tu ning cu rve fo r a st ep tu ned vc o is sh own in figure 30 . note how the tuning voltage stays in a narrow range over a wide range of output frequencies. 0 1 2 3 4 5 920 960 1000 1040 1080 1120 1160 calibration frequency (mhz) tune voltage after calibration (v) 50mhz pfd, 500khz tuning steps, +25c 256 count calibration ,195khz resolution 31usec total cal time 0 15 31 figure 30. a typical 5-bit 32 switch vco tuning voltage after calibration the calibration is no rmally ru n au tomatically on ce fo r ev ery ch ange of fre quency. th is en sures op timum selection of vc o sw itch se ttings vs . ti me an d te mperature. th e us er do es no t no rmally ha ve to be co ncerned about which sw itch se tting is us ed fo r a gi ven fre quency as th is is ha ndled by th e au tocal ro utine. th e accuracy required in th e ca libration aff ects th e am ount of ti me re quired to tu ne th e vc o. th e ca libration routine searches fo r th e be st st ep se tting th at lo cks th e vc o at th e cu rrent pr ogrammed fre quency, an d ensures that th e vc o wi ll st ay lo cked an d pe rform we ll ov er it s fu ll te mperature ra nge wi thout ad ditional calibration, regardless of the temperature that the vco was calibrated at. auto-calibration ca n al so be di sabled al lowing ma nual vc o tu ning. re fer to se ction 1.2.2 for a d escription of manual tuning 1.2.1.1 autocal use of reg05h autocal transfers sw itch co ntrol da ta to th e vc o su bsystem vi a reg 05h . the address of th e vc o subsystem in reg 05h is not altered by th e au tocal ro utine. th e ad dress an d id of th e vc o su bsystem in reg 05h must be set to th e co rrect va lue be fore au tocal is ex ecuted. fo r mo re in formation se e se ction 1.19 . 1.2.1.2 auto-relock on lock detect failure it is possible by se tting reg 07h [13] to have the vc o su bsystem au tomatically re -run th e ca libration routine and re -lock it self if lo ck de tect in dicates an un locked co ndition fo r an y re ason. wi th th is op tion th e system will attempt to re-lock only once. auto-relock is recommended. 1.2.2 manual vco calibration for fast frequency hopping if it is desirable to sw itch fre quencies ve ry qu ickly it is po ssible to el iminate th e au tocal ti me by ca librating the vco in ad vance an d sto ring th e sw itch nu mber vs fre quency in formation in th e ho st. th is ca n be do ne by initially lo cking th e pl l wi th in tegrated vc o on ea ch de sired fre quency us ing au tocal, th en re ading, and storing th e vc o sw itch se ttings se lected. th e vc o sw itch se ttings ar e av ailable in reg 10h [7:0] after every autocal op eration. th e ho st mu st th en pr ogram th e vc o sw itch se ttings di rectly wh en ch anging frequencies. ma nual wr ites to th e vc o sw itches ar e ex ecuted im mediately as ar e wr ites to th e in teger an d fractional registers wh en au tocal is di sabled. he nce fre quency ch anges wi th ma nual co ntrol an d au tocal disabled, requires a mi nimum of two se rial po rt tr ansfers to th e pl l, on ce to se t th e vc o sw itches, an d once to set the pll frequency. if autocal is di sabled reg 0ah [11]=1 , the vco wi ll up date it s re gisters wi th th e va lue wr itten vi a reg 05h immediately. th e vc o in ternal tr ansfer re quires 16 vs ck cl ock cy cles aft er th e co mpletion of a wr ite to plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 18 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz reg 05h . vsck and th e au tocal co ntroller cl ock ar e eq ual to th e in put re ference di vided by 0, 4, 16 or 32 as controlled by reg 0ah [14:13] . 1.2.2.1 registers required for frequency changes in fractional mode a large change of frequency, in fractional mode ( reg 06h [11]=1 ), may require main serial port writes to: 1. the integer register intg, reg 03h (only required if the integer part changes) 2. the vco spi register, reg 05h ? required for manual control of vco if reg 0ah [11]=1 (autocal disabled) ? required to change the rf divider value if needed ( vco_reg 02h biases ) ? required to turn on/off the doubler mode if needed ( vco_reg 03h [0]) 3. the fractional re gister, reg 04h . the fractional re gister wr ite tr iggers au tocal if reg 0ah [11]= 0 , and is loaded into th e mo dulator au tomatically aft er au tocal ru ns. if au tocal is di sabled, reg 0ah [11]=1 , the fractional fre quency ch ange is lo aded in to th e mo dulator im mediately wh en th e re gister is wr itten with no adjustment to the vco. small steps in fre quency in fra ctional mo de, wi th au tocal en abled ( reg 0a h [11]= 0 ), usually only re quire a single write to th e fra ctional re gister. wo rst ca se, 5 ma in se rial po rt tr ansfers to th e hm c833lp6ge co uld be required to ch ange fre quencies in fra ctional mo de. if th e fre quency st ep is sm all an d th e in teger pa rt of the frequency do es no t ch ange, th en th e in teger re gister is no t ch anged. in al l ca ses, in fra ctional mo de, it is necessary to write to the fractional register reg 04h for frequency changes. 1.2.2.2 registers required for frequency changes in integer mode a change of frequency, in integer mode ( reg 06h [11]= 0) , requires main serial port writes to: 1. vco spi register, reg 05h ? required for manual control of vco if reg 0ah [11]=1 (autocal disabled) ? required to change the rf divider value if needed ( vco_reg 02h biases ) ? required to turn on/off the doubler mode if needed ( vco_reg 03h [0]) 2. the integer register reg 03h . ? in integer mo de, an in teger re gister wr ite tr iggers au tocal if reg 0ah [11]= 0 , and is loaded in to the prescaler au tomatically aft er au tocal ru ns. if au tocal is di sabled, reg 0ah [11]=1 , the integer frequency ch ange is lo aded in to th e pr escaler im mediately wh en wr itten wi th no ad justment to the vco. no rmally ch anges to th e in teger re gister ca use la rge st eps in th e vc o fre quency, hence the vc o sw itch se ttings mu st be ad justed. au tocal en abled is th e re commended me thod for integer mo de fre quency ch anges. if au tocal is di sabled ( reg 0ah [11]=1 ), a priori knowledge of the correct vc o sw itch se tting an d th e co rresponding ad justment to th e vc o is re quired before executing the integer frequency change. 1.2.3 vco autocal on frequency change assuming reg 0ah [11]= 0 , the vco ca libration st arts au tomatically wh enever a fre quency ch ange is requested. if it is de sired to re run th e au tocal ro utine fo r an y re ason, at th e sa me fre quency, si mply re write the frequency ch ange wi th th e sa me va lue an d th e au tocal ro utine wi ll ex ecute ag ain wi thout ch anging fnal frequency. plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 19 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz 1.2.4 vco autocal time & accuracy the vco frequency is counted for t mmt , the period of a single autocal measurement cycle. t mmt = t xtal r 2 n (eq 1) n is se t by reg 0ah [2:0] and r esults i n m easurement p eriods w hich a re m ultiples o f t he p d period, t xtal r . r is the reference path division ratio currently in use, reg 02h t xtal is the period of the external reference (crystal) oscillator. the vco au tocal co unter wi ll, on av erage, ex pect n co unts, ro unded do wn (f oor) to th e ne arest in teger, every pd cycle. n is the ratio of the target vco frequency, f vco , to the frequency of the pd, f pd , where n can be any rational number supported by the n divider. n is set by the integer ( n int = reg 03h ) and fractional ( n frac = reg 04h ) register contents n = n int + n frac / 2 24 (eq 2) the autocal st ate ma chine an d th e da ta tr ansfers to th e in ternal vc o su bsystem sp i (v spi) ru n at th e ra te of the fsm clock, t fsm , where the fsm clock frequency cannot be greater than 50 mhz. t fsm = t xtal 2 m (eq 3) m is 0, 2, 4 or 5 as determined by reg 0ah [14:13] the expected number of vco counts, v, is given by v = foor (n 2 n ) (eq 4) the nominal vco frequency measured, f vcom , is given by f vcom = v f xtal / (2 n r) (eq 5) where the worst case measurement error, f err , is: f err f pd / 2 n + 1 (eq 6) figure 31. vco calibration a 5-bit step tu ned vc o, fo r ex ample, no minally re quires 5 me asurements fo r ca libration, wor st ca se 6 measurements, an d he nce 7 vs pi da ta tr ansfers of 20 cl ock cy cles ea ch. th e me asurement ha s a programmable nu mber of wa it st ates, k, of 10 0 fs m cy cles de fned by reg 0ah [7:6] = k. he nce tot al calibration time, worst case, is given by: t cal = k128t fsm + 6t pd 2 n + 7 20t fsm (eq 7) plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 20 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz or equivalently t cal = t xtal (6r 2 n + (140+128k) 2 m ) where k = reg 0ah [7:6] decimal (eq 8) for guaranteed ho ld of loc k, ac ross te mperature ex tremes, the re solution sho uld be bet ter tha n 1/8 th the frequency st ep ca used by a vc o su b-band sw itch ch ange. be tter re solution se ttings wi ll sh ow no improvement. 1.2.4.1 vco autocal example the vco subsystem must satisfy the maximum f pd limited by the two following conditions: a. n 16 (f int ), n 20.0 (f frac ), where n = f vco/ f pd b. f pd 100 mhz suppose the vc o su bsystem ou tput fre quency is to op erate at 2. 01 gh z. ou r ex ample cr ystal fre quency is f xtal = 50 mhz, r=1, and m=0 ( figure 31 ) , hence t fsm = 20 ns (50 mh z). no te, wh en us ing au tocal, th e maximum au tocal fi nite st ate ma chine (f sm) cl ock ca nnot ex ceed 60 mh z (s ee reg 0ah [14:13] ). the fsm clock do es no t aff ect th e ac curacy of th e me asurement, it on ly aff ects th e ti me to pr oduce th e re sult. this same clock is used to clock the 16 bit vco serial port. if time to change fre quencies is no t a co ncern, th en on e ma y se t th e ca libration ti me fo r ma ximum ac curacy, and therefore not be concerned with measurement resolution. using an input cr ystal of 50 mh z (r =1 an d fp d=50 mh z) th e ti mes an d ac curacies fo r ca libration us ing (eq 6) and (eq 8) are shown in table 1 . where minimal tuning time is 1/8 th of the vco band spacing. across all vc os, a me asurement re solution be tter th an 80 0 kh z wi ll pr oduce co rrect re sults. se tting m = 0, n = 5, pr ovides 78 1 kh z of re solution an d ad ds 8. 6 s of au tocal ti me to a no rmal fre quency ho p. once the au tocal se ts th e fn al sw itch va lue, 8. 64 s aft er th e fre quency ch ange co mmand, th e fra ctional register will be lo aded, an d th e lo op wi ll lo ck wi th a no rmal tr ansient pr edicted by th e lo op dy namics. he nce we can see in th is ex ample th at au tocal ty pically ad ds ab out 8. 6 s to th e no rmal ti me to ac hieve fre qu- ency lock. hence, autocal should be used for all but the most extreme frequency hopping requirements. table 1. autocal example with f xtal = 50 mhz, r = 1, m = 0 control value reg0ah[2:0] n 2 n t mmt (s) t cal (s) f err max 0 0 1 0.02 4.92 25 mhz 1 1 2 0.04 5.04 12.5 mhz 2 2 4 0.08 5.28 6.25 mhz 3 3 8 0.16 5.76 3.125 mhz 4 5 32 0.64 8.64 781 khz 5 6 64 1.28 12.48 390 khz 6 7 128 2.56 20.16 195 khz 7 8 256 5.12 35.52 98 khz 1.2.5 vco output mute function the output mu te fu nction en ables th e hm c833lp6ge to di sable th e vc o ou tput wh ile ma intaining th e pl l and vco subsystems fu lly fu nctional. th e mu te fu nction pr ovides ov er 40 db of is olation th roughout th e operating range of th e hm c833lp6ge. to mu te th e ou tput of th e hm c833lp6ge, th e fo llowing re gister writes are necessary: 1. initially, and on ly on ce, ty pically aft er po wer-up, pr e-confgure th e vc o su bsystem by wr iting vco_ reg 01h [8:0] = 3h (a ccomplished by wr iting to reg 05h = 188h). th is wr ite ef fectively en ables th e master enable, an d pl l bu ffer en able, an d di sables th e ma nual mo de rf bu ffer, di vide-by 1, an d rf plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 21 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz divider of the vc o su bsystem, as sh own in figure 27 . although this wr ite dis ables the man ual mo de enables o f t he v co s ubsystem, i t ha s n o a ffect o n t he p ll o r v co s ubsystem b ecause t ypically a nd by default the vco subsystem is operating in auto mode. 2. then to mute th e pl l ou tput si mply wr ite vco_reg 0 3h [ 2] = 1 (accomplish by wr iting to pl l reg 0 5h = 2218h in do ubler mo de, an d reg 05h = 2 a98h i n f undamental m ode o f t he v co), w hich e ffectively places the vc o su bsystem in ma nual mo de. ma nual mo de en ables ha ve be en pr e-confgured in st ep 1 to mute the pll output. 3. if it is required to tu ne th e hm c833lp6ge wh ile th e ou tput is mu ted a fn al wr ite, reg 05h = 0h, is required. to enable the HMC833LP6GE output after muting: 1. write vco_reg 03 h [ 2] = 0 (accomplish by wr iting to pl l reg 05h = 2018h in do ubler mo de, or reg 05h = 2898h in fundamental mode). 2. a fnal write to reg 05h = 0h is required. please refer to figure 27 for more information. al so no te th at th e vc o su bsystem re gisters ar e no t di rectly accessible. th ey ar e wr itten to th e vc o su bsystem vi a pl l reg 05h . more information ab out vc o subsystem spi in section 1.19 . 1.3 vco built in test with autocal the frequency limits of the vco can be measured using the bist features of the autocal machine. this is done by se tting reg 0ah [10]=1 which fre ezes th e vc o sw itches in on e po sition. vc o sw itches ma y then be written ma nually, wi th th e va ractor bi ased at th e no minal mi d-rail vo ltage us ed fo r au tocal. fo r example to me asure th e vc o ma ximum fre quency us e sw itch 0, wr itten to th e vc o su bsystem vi a reg 05h =[000000000 0000 vc oid]. wh ere vc oid = 000 b. if autocal is en abled, ( reg 0ah [11] = 0), and a ne w fre quency is wr itten, au tocal wi ll ru n, bu t wi th sw itches frozen. the vc o fre quency er ror re lative to th e co mmand fre quency wi ll be me asured an d re sults wr itten to re g 11h [19:0] where re g 11h [19] is the si gn bi t. th e re sult wi ll be wr itten in te rms of vc o co unt er ror (eq 4) . for example if th e ex pected vc o is 2 gh z, re ference is 50 mh z, an d n is 6, we ex pect to me asure 2560 counts. if we me asure a di fference of -5 co unts in re g 11h , then it means we ac tually me asured 25 55 counts. hence the actual frequency of the vco is 5/2560 low, or 1.99609375 ghz, 1 count ~ 781 khz. 1.4 spurious performance 1.4.1 integer operation and reference spurious the v co a lways o perates a t a n i nteger m ultiple o f t he p d f requency i n a n i nteger s ynthesizer. i n g eneral, spurious signals or iginating fro m an in teger sy nthesizer ca n on ly oc cur at mu ltiples of th e pd fre quency. these unwanted ou tputs cl osest to th e ca rrier ar e of ten si mply re ferred to as re ference si debands. unwanted reference harmonics can also exist far from the carrier due to circuit isolation. spurs unrelated to th e re ference fre quency mu st or iginate fro m ou tside so urces. ex ternal sp urious so urces can modulate th e vc o in directly th rough po wer su pplies, gr ound, or ou tput po rts, or by pass th e lo op fl ter due to poor isolation of the flter. it can also simply add to the output of the pll. reference sp uri ou s le vels ar e ty pically be low -1 00 db c wi th a we ll de signed bo ard la yout. a re gulator wi th low noise an d hi gh po wer su pply re jection, su ch as th e hm c1060lp3e, is re commended to mi nimize external spurious sources. reference s purious l evels o f b elow - 100 d bc r equire s uperb b oard i solation o f p ower s upplies, i solation o f the vco from th e di gital sw itching of th e sy nthesizer an d is olation of th e vc o lo ad fro m th e sy nthesizer. typical board la yout, re gulator de sign, ev al bo ards an d ap plication in formation ar e av ailable fo r ve ry lo w spurious operation. ope ration wi th low er le vels of iso lation in the appl ication ci rcuit bo ard, fr om tho se re c - ommended by hittite, can result in higher spurious levels. plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 22 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz if the application en vironment co ntains ot her in terfering fre quencies un related to th e pd fre qu ency, an d if the application is olation fro m th e bo ard la yout an d re gulation ar e in sufficient, th e un wanted in terfering frequencies wi ll mix wi th th e desi red syn thesizer ou tput an d ca use ad ditional sp urious emi ssions. th e level of these emissions is dependant upon isolation and supply regulation or rejection (psrr). 1.4.2 fractional operation and spurious unlike an integer pl l, sp urious si gnals in a fra ctional pl l ca n oc cur du e to th e fa ct th at th e vc o op erates at frequencies un related to th e pd fre quency. he nce in termodulation of th e vc o an d th e pd ha rmonics can cause sp urious si debands. sp urious em issions ar e la rgest wh en th e vc o op erates ve ry cl ose to an integer multiple of th e pd . wh en th e vc o op erates ex actly at a ha rmonic of th e pd th en, no in -close mi xing products are present. as shown in figure 32 , interference is al ways pr esent at mu ltiples of th e pd fre quency, f pd , and the vco frequency, f vco . the difference, , be tween th e vc o fre quency an d th e ne arest ha r mo nic of th e re ference, will create wh at ar e re ferred to as in teger bo undary sp urs. de pending up on th e mo de of op eration of the synthesizer, hi gher or der, lo wer po wer sp urs ma y al so oc cur at mu ltiples of in teger fra ctions (s ub- harmonics) of th e pd fre quency. th at is , fra ctional vc o fre quencies wh ich ar e ne ar nf pd + f pd d/m, where n, d and m are al l in tegers an d d< m (m athematicians re fer to d/ m as a ra tional nu m be r). we wi ll re fer to f pd d/m as an integer fra ction. th e de nominator, m, is th e or der of th e sp urious pr oduct. hi gher va lues of m pr oduce smaller amplitude spurious at offsets of m and usually when m>4 spurs are small or unmeasurable. the worst ca se, in fra ctional mo de, is wh en d= 0, an d th e vc o fre quency is of fset fro m nf pd by less than the loop bandwidth. this is the in-band integer boundary case. figure 32. fractional spurious example characterization of th e le vels an d or ders of th ese pr oducts is no t un like a mi xer sp ur ch art. ex act le vels of the products ar e de pendent up on is olation of th e va rious sy nthesizer pa rts. hi ttite ca n of fer gu idance about expected le vels of sp urious wi th hm c833lp6ge ev aluation bo ards. re gulators wi th hi gh po wer supply rejection ratios (psrr) are recommended, especially in noisy applications. 1.4.2.1 charge pump and phase detector spurious considerations charge pump an d ph ase de tector li nearity ar e of pa ramount im portance wh en op erating in fra ctional mode. any non-linearity degrades phase noise and spurious performance. plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 23 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz we defne ze ro ph ase er ror wh en th e re ference si gnal an d th e di vider vc o si gnal ar rive at th e ph ase detector at th e sa me ti me. ph ase de tector li nearity de grades wh en th e ph ase er ror is ve ry sm all an d when the random ph ase er rors ca use th e ph ase de tector to sw itch ba ck an fo rth be tween re ference le ad and vco lead. these switching no n-linearities in fra ctional mo de ar e el iminated by op erating th e ph ase de tector wi th an average phase offset such that either the reference or vco always leads. a programmable ch arge pu mp of fset cu rrent so urce is us ed to ad d dc cu rrent to th e lo op fl ter an d cr eate the desired ph ase of fset. po sitive cu rrent ca uses th e vc o to le ad, ne gative cu rrent ca uses th e re ference to lead. the offset ch arge pu mp is co ntrolled vi a reg 09h . the phase of fset is sc aled fro m 0 de grees, th at is th e reference an d th e vc o pa th ar rive in ph ase, to 36 0 de grees, wh ere th ey ar rive a fu ll cy cle la te. th e of fset can also be thought of in absolute time difference between the arrivals. the r ecommended o perating p oint f or t he c harge pu mp in f ractional m ode i s o ne w here t he t ime o ffset a t the phase de tector is ~2 .5ns + 4t vco , where t vco is the rf pe riod at th e fra ctional pr escaler in put. th e required cp offset current should never exceed 25% of the programmed cp current. the specifc le vel of ch arge pu mp of fset cu rrent reg 09h [20:14] is de termined by th is ti me of fset, th e comparison frequency and the charge pump current: ( ) ( ) ( ) 9 2.5 10 4 sec ,0.25 required cp offset min vco comparison cp cp t fi i ? ?? ? +? ? ? ? ?? ?? = where: t vco : is the rf period at the fractional prescaler input i cp : is the full scale current setting of the switching charge pump reg 09h [6:0] reg 09h [13:7] (eq 9) operation w ith c harge p ump o ffset i nfuences t he r equired c onfguration o f t he l ock d etect f unction. r efer to the description of lo ck de tect fu nction in se ction 1.11 . note that th is ca lculation ca n be pe rformed fo r the center fre quency of th e vc o, an d do es no t ne ed re fnement fo r sm all di fferences < 25 % in ce nter frequencies. another factor in th e sp ectral pe rformance in fr actional mo de is th e ch oice of th e de lta-sigma mo dulator mode. mode a ca n of fer be tter in -band sp ectral pe rformance (i nside th e lo op ba ndwidth) wh ile mo de b offers better ou t of ba nd pe rformance. se e reg 06h [3:2] for dsm mo de se lection. fi nally, al l fra ctional synthesizers cr e at e fra ctional sp urs at so me le vel. hi ttite of fers th e lo west le vel fra ctional sp urious in th e indus try i n a n i ntegrated s olution. 1.4.2.2 spurious related to channel step size (channel spurs) many fractional pl ls al so cr eate sp urious em issions at of fsets wh ich ar e mu ltiples of th e ch annel st ep size. we refer to th ese as ch annel sp urs. it is co mmon in th e in dustry to se t th e ch annel st ep si ze by us e of the so-called mo dulus. fo r ex ample, ch annel st ep si ze of 10 0 kh z re quires a sm all mo dulus re lated to the step size, and often results in 100 khz channel spurs. the HMC833LP6GE us es a la rge fx ed mo dulus un related to th e ch annel st ep si ze. as a re sult, th e HMC833LP6GE ha s ex tremely lo w or un measurable ch annel sp urs. in ad dition ex act fr equency mo de ( 1.12.2.2 ) allows exact channel step size with no channel spurs. the lack of ch annel sp urs me ans th at th e hm c833lp6ge ha s la rge re gions of op eration be tween in teger boundaries wi th li ttle or no sp urs of an y ki nd. la rge sp urious fre e zo nes en able th e hm c833lp6ge to be used with a tu nable re ference, to ef fectively mo ve th e sp ur fre e zo nes an d he nce ac hieve sp ur-free operation at all frequencies. the resulting pll is virtually spur-free at all frequencies. for more information see 1.4.2.3 . plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 24 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz 1.4.2.3 spurious reduction with tunable reference section 1.4.2 discussed fra ctional mo de in teger bo undary sp urious ca used by vc o ope ration ne ar reference ha rmonics. it is po ssible, wi th hi ttite fra ctional sy nthesizers, to vi rtually el iminate th e in teger boundary sp urious at a gi ven vc o fre quency by ch anging th e fre quency of th e re ference. th e re ference frequency is no rmally ge nerated by a cr ystal os cillator an d is no t tu nable. ho wever, an y of hi ttites wi deband plls with in tegrated vc os, in cluding hm c833lp6ge, ca n be us ed as a hi gh-quality tu nable re ference source, as shown in figure 33 . figure 33. tunable r eference s ource with the setup sh own in figure 33 , the HMC833LP6GE is ca pable of op erating ac ross al l of it s fre quency range without sa crifcing pha se no ise, wh ile vir tually el iminating sp urious em issions. op timum ope ration requires appropriate co nfguration of th e two sy nthesizers to ac hieve th is pe rformance. hi ttite ap ps-support can assist with the required algorithms for ultra-low spurious tunable reference applications. an HMC833LP6GE tu nable re ference pl l ty pically us es a hi gh fre quency cr ystal re ference fo r be st performance. ph ase no ise fro m th e mc 830lp6ge tu nable re ference ou tput at 10 0 kh z of fset va ries ty pically from -145 dbc at 10 0 mh z ou tput to -1 57 db c at 25 mh z ou tput. th is pe rformance of hm c833lp6ge as a tunable reference is equivalent to the phase noise of high performance crystal oscillators. figure 34. phase noise performance of the HMC833LP6GE -170 -160 -150 -140 -130 -120 0.1 1 10 100 1000 10000 100000 carrier frequency = 25 mhz carrier frequency = 55.55 mhz carrier frequency = 100 mhz phase noise (dbc/hz) offset (khz) when used with a tunable reference source. (HMC833LP6GE operating at 3 ghz/30, 3 ghz/54, and 1.55 ghz/62 for the 100 mhz, 55.55 mhz, and 25 mhz curves respectively.) worst case sp urious le vels (l argest sp urs at an y of fset) of co nventional fx ed re ference vs . a tu nable reference ca n be co mpared by mu ltiple in dividual ph ase no ise me asurements an d su mmarized on a si ngle plot vs. carrier frequency. for example, figure 35 shows the sp ectrum of a ca rrier op erating at 20 00.1 mh z wi th a 50 mh z fx ed reference. th is ca se is 10 0 kh z aw ay fro m an in teger bo undary (5 0 mh z x 40 ). wo rst ca se sp urious ca n be observed at 100 khz offset and about -52 dbc in magnitude. figure 36 shows the sa me hm c833lp6ge pl l vc o op erating at th e sa me 20 00.1 mh z ca rrier fre quency, using a t unable r eference a t 4 7.5 m hz g enerated b y h mc830lp6ge. w orst c ase s purious i n t his c ase c an be observed at 5 mhz offset and about -100 dbc in magnitude. the results of figure 35 and figure 36 show that th e tu nable re ference so urce ac hieves 50 db be tter spurious performance, while maintaining essentially the same phase noise performance. plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 25 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz -180 -160 -140 -120 -100 -80 -60 -40 -20 0 0.1 1 10 100 1000 10000 100000 phase noise (dbc/hz) offset (khz) (a) 2000.1 mhz carrier frequency worst spur at 100 khz offset at ~-52 dbc with 50 mhz crystal -180 -160 -140 -120 -100 -80 -60 -40 -20 0 0.1 1 10 100 1000 10000 100000 phase noise (dbc/hz) offset (khz) 2000.1 mhz carrier frequency worst spur at 5.1 mhz offset at -100 dbc with tunable reference (b) figure 35. HMC833LP6GE worst spur at any offset, fxed 50 mhz reference, output frequency = 2000.1 mhz figure 36. hm c833lp6ge worst spur at any offset, tunable reference (hmc830lp6ge), output frequency = 2000.1 mhz many spurious me asurements, su ch as th e on es in figure 35 and figure 36 can be summarized in to a single plot of wor st ca se sp urious at an y of fset vs . ca rrier fre quency as sh own in figure 37 . a log frequency display relative to th e 20 00 mh z fx ed re ference in teger bo undary wa s us ed to em phasize th e im portance of t he l oop b andwidth on s purious p erformance o f t he f xed r eference c ase. t his t echnique c learly s hows the logarithmic ro ll-off of th e wor st ca se sp urious wh en op erating ne ar th e in teger bo undary. in th is ca se the loop flter bandwidth of the HMC833LP6GE was 100 khz. figure 37. -120 -110 -100 -90 -80 -70 -60 -50 2ghz +1khz 2ghz +10khz 2ghz +100khz 2ghz +1000khz 2ghz +10000k fixed 50 mhz reference tunable reference worst spur (dbc) output frequency (a) (b) largest observed spurious, at any offset, using a fxed 50 mhz reference source and a tunable reference source. for example wor st ca se sp urious op erating at 20 00.1 mh z (p oint (a )) in figure 35 with a fxed 50 mh z reference) i s r epresented b y a s ingle p oint in figure 37 (point ( a)) o n t he b lue c urve. s imilarly, w orst c ase spurious from figure 36 with v ariable r eference, o perating a t 20 00.1 m hz i s r epresented b y a s ingle p oint in figure 37 (point (b)) on the green curve. the plot in figure 37 is generated by tu ning th e ca rrier fre quency aw ay fro m in teger bo undary an d recording the wor st ca se sp urious, at an y of fset, at ea ch op erating fre quency. figure 37 shows that th e worst case sp urious fo r th e 50 mh z fx ed re ference ca se, is ne arly co nstant be tween -5 1 db c an d -5 5 dbc when op erating wi th a ca rrier fre quency le ss th an 10 0 kh z fro m th e in teger bo undary (bl ue cu rve). it also shows th at th e wor st ca se sp urious ro lls of f at ab out 25 db /decade re lative to 1 lo op ba ndwidth. for example, at an op erating fre quency of 20 01 mh z (e quivalent to 10 lo op ba ndwidths of fset) wor st ca se spurious is -8 0 db c. si milarly, at an op erating fre quency of 20 10 mh z (e quivalent to 10 0 lo op ba ndwidths) worst case spurious is -100 dbc. plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 26 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz in contrast, th e gr een cu rve of figure 37 shows that th e wor st ca se sp urious ov er th e sa me op erating frequency ra nge, wh en us ing an hm c830lp6ge tu nable re ference, is be low -1 00 db c at al l op erating frequencies! in general al l fra ctional pl ls ha ve sp urious wh en op erating ne ar in teger bo undaries. hi gh pe rformance tunable r eference m akes i t p ossible t o o perate h mc833lp6ge, v irtually s pur-free a t a ll f requencies, wi th little or no degradation in phase noise. 1.5 integrated phase noise & jitter the standard de viation of vc o si gnal ji tter ma y be es timated wi th a si mple ap proximation if it is as sumed that the locked vc o ha s a co nstant ph ase no ise, o | 2 ( f o ), at offsets le ss th an th e lo op 3 db ba ndwidth an d a 20 d b p er d ecade r oll-off a t g reater o ffsets. t he s imple l ocked v co p hase n oise a pproximation i s s hown on the left of figure 38 . figure 38. pll with integrated vco phase noise & jitter with this simplifcation the total integrated vco phase noise, o | 2 , in rads 2 in the linear form is given by o | 2 = o | 2 (f o ) b (eq 10) where o | 2 (f o ) is the single sideband phase noise in rads 2 /hz inside the loop bandwidth, and b is the 3 db corner frequency of the closed loop pll the integrated phase noise at the phase frequency detector, o | 2 pd is just scaled by n 2 /n 2 = o | 2 pd o | 2 (eq 11) the rms phase jitter of the vco in rads, o | , i s j ust t he s quare r oot o f t he p hase n oise i ntegral. since the si mple in tegral of (eq 10) is j ust a p roduct o f c onstants, w e ca n e asily d o t he i ntegral i n t he l og domain. f or e xample i f t he v co p hase no ise i nside t he l oop i s - 100 d bc/hz a t 1 0 k hz o ffset a nd t he l oop bandwidth is 10 0 kh z, an d th e di vision ra tio is 10 0, th en th e in tegrated ph ase no ise at th e ph ase fre quency detector, in db, is given by: o | 2 = 10log ( o | 2 ( f o )b/n 2 ) = -100 + 50 + 5 - 40 = -85 dbc pddb or equivalently, o | = 1 0 -85/20 = 53.6e-6 rads = 3.2e-3 degrees. while the ph ase no ise re duces by a fa ctor of 20 logn aft er di vision to th e re ference, du e to th e in creased period of the pd reference signal, the jitter is constant. the rms jitter from the phase noise is then given by t jpn = t pd o | pd /2 (eq 12) in this example if the pd reference was 50 mhz, t pd = 20ns, and hence t jpn = 179 femto-sec. it should be no ted th at th is la st ex pression is ba sed up on a cl osed fo rm in tegral of th e en tire sp ectrum of the oscillator ph ase no ise. th is in tegral st arts at dc . it is co mmon fo r re al sys tem to ev aluate ji tter ov er shorter intervals of ti me, he nce th e in tegral of ten st arts at so me fn ite fre quency of fset an d wi ll pr oduce a plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 27 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz jitter that is le ss th an th at gi ven by th e fu ll ex pression. fi nally re al os cillators ha ve no ise fo ors th at al so contribute to ji tter. th e ph ase no ise of a wh ite no ise fo or is a si mple in tegral of no ise fo or de nsity ti mes bandwidth of in terest to th e sys tem. th is ad ditional no ise po wer sh ould be ad ded to th e ex pression of (eq 16) to give a mo re ac curate ji tter nu mber. de pending up on th e ba ndwidth of th e sys tem in qu estion this noise foor contribution may be an important factor. 1.6 reference input stage figure 39. reference path input stage the reference bu ffer pr ovides th e pa th fro m an ex ternal re ference so urce (g enerally cr ystal ba sed) to the r divider, an d ev entually to th e ph ase de tector. th e bu ffer ha s two mo des of op eration co ntrolled by reg 0 8h [21]. h igh g ain ( reg 0 8h [21] = 0 ), r ecommended b elow 2 0 0 m hz, a nd h igh f requency ( reg 0 8h [ 2 1 ] = 1 ), f or 2 00 t o 3 50 m hz o peration. t he b uffer i s i nternally d c b iased, w ith 1 00 i nternal te rmination. f or 50 match, an ex ternal 10 0 re sistor to gr ound sh ould be ad ded, fo llowed by an ac co upling ca pacitor (impedance < 1 ), then to the xrefp pin of the part. at low frequencies, a re latively sq uare re ference is re commended to ke ep th e in put sl ew ra te hi gh. at hi gher frequencies, a sq uare or si nusoid ca n be us ed. th e fo llowing ta ble sh ows th e re commended op erating regions for di fferent re ference fre quencies. if op erating ou tside th ese re gions th e pa rt wi ll no rmally st ill operate, but with degraded reference path phase noise performance. minimum pulse wi dth at th e re ference bu ffer in put is 2. 5 ns . fo r be st sp ur pe rformance wh en r = 1, th e pulse w idth s hould b e ( 2.5ns + 8 t ps ), w here t ps is t he p eriod o f t he v co a t t he p rescaler i nput. w hen r > 1 minimum pulse width is 2.5 ns. table 2. reference sensitivity table square input sinusoidal input reference input frequency (mhz) slew > 0.5v/ns recommended swing (vpp) recommended po wer range (dbm) recommended min max recommended min max < 1 0 yes 0.6 2.5 x x x 10 yes 0.6 2.5 x x x 25 yes 0.6 2.5 ok 8 15 50 yes 0.6 2.5 yes 6 15 100 yes 0.6 2.5 yes 5 15 150 ok 0.9 2.5 yes 4 12 200 ok 1. 2 2.5 yes 3 8 input referred ph ase no ise of th e pl l wh en op erating at 50 mh z is be tween -1 50 an d -1 56 db c/hz at plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 28 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz 10 khz offset de pending up on th e mo de of op eration. th e in put re ference si gnal sh ould be 10 db be tter than this foor to av oid de g ra dation of th e pl l no ise co ntribution. it sh ould be no ted th at su ch lo w le vels are only necessary if th e pl l is th e do minant no ise co ntributor an d th ese le vels ar e re quired fo r th e sys tem goals. 1.7 reference path r divider the reference pa th r di vider is ba sed on a 14 -bit co unter an d ca n di vide in put si gnals by va lues fro m 1 to 16,383 and is controlled by rdiv ( reg 02h ). minimum pulse wi dth at th e re ference bu ffer in put is 2. 5 ns . fo r be st sp ur pe rformance wh en r = 1, th e pulse w idth s hould b e ( 2.5 ns + 8 tps), wh ere t ps i s t he p eriod o f t he v co a t t he p rescaler i nput. w hen r > 1 minimum pulse width is 2.5 ns. 1.8 rf path n divider the main rf pa th di vider is cap able of av erage di vide ratio s bet ween 2 19 -5 (524,283) an d 20 in fra ctional mode, and 2 19 -1 (524,287) to 16 in in teger mo de. th e vc o fre quency ra nge di vided by th e mi nimum n divider value wi ll pl ace pr actical re strictions on th e ma ximum us able pd fre quency. fo r ex ample a vc o operating at 1. 5 gh z in fra ctional mo de wi th a mi nimum n di vider va lue of 20 wi ll ha ve a ma ximum pd frequency of 75 mhz. 1.9 charge pump & phase detector the phase de tector (p d) ha s two in puts, on e fro m th e re ference pa th di vider an d on e fro m th e rf pa th divider. when in lo ck th ese two in puts ar e at th e sa me av erage fre quency an d ar e fx ed at a co nstant average phase of fset wi th re spect to ea ch ot her. we re fer to th e fre quency of op eration of th e pd as f pd . most formulae re lated to st ep si ze, de lta-sigma mo dulation, ti mers et c., ar e fu nctions of th e op erating frequency of the pd, f pd . f pd is also referred to as the comparison frequency of the pd. the pd compares th e ph ase of th e rf pa th si gnal wi th th at of th e re ference pa th si gnal an d co ntrols th e charge pump ou tput cu rrent as a li near fu nction of th e ph ase di fference be tween th e two si gnals. th e output current varies linearly over a full 2 radians (360) of input phase difference. 1.10 phase detector functions phase detector register reg 0bh allows manual access to control special phase detector features. pd_up_en ( reg 0 bh [5]), if 0, masks the pd up ou tput, wh ich pr events th e ch arge pu mp fro m pu mping up .` pd_dn_en ( reg 0bh [6]), if 0, masks the pd do wn ou tput, wh ich pr events th e ch arge pu mp fro m pu mping down. clearing both pd_up_en and pd_dn_en effectively tr i-states th e ch arge pu mp whi le lea ving al l ot her functions operating int ernally. pd force up reg 0 bh [9] = 1 and p d f orce d n reg 0 bh [10] = 1 allows the ch arge pu mp to be fo rced up or down respectively. th is wi ll fo rce th e vc o to th e en ds to th e tu ning ra nge wh ich ca n be us eful in te st of the vco. 1.11 phase detector window based lock detect lock detect enable reg 07h [3]=1 is a global enable for all lock detect functions. the window ba sed lo ck de tect ci rcuit ef fectively me asures th e di fference be tween th e ar rival of th e reference an d th e di vided vc o si gnals at th e pd . th e ar rival ti me di fference mu st co nsistently be le ss than the lock de tect wi ndow le ngth, to de clare lo ck. ei ther si gnal ma y ar rive fr st, on ly th e di fference in arrival times is counted. plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 29 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz 1.11.1 analog window lock detect the l ock d etect w indow m ay b e g enerated b y e ither a n a nalog o ne s hot c ircuit o r a d igital o ne s hot b ased upon an internal ti mer. se tting reg 07h [6]=0 will result in a fx ed, an alog, no minal 10 ns wi ndow, as sh own in figure 40 . the analog wi ndow ca nnot be us ed if th e pd ra te is ab ove 50 mh z, or if th e of fset is too la rge. figure 40. normal lock detect window - integer mode, zero offset for ex ample a 2 5 m hz p d r ate w ith a 1 m a c harge p ump s etting ( reg 09h [6:0]= reg 09h [13:7]= 32h) and 400 a offset do wn cu rrent ( reg 09h [20:14]= 50h reg 09h [22]= 1) , would have an of fset of ab out 40 0/1000 = 40% of the pd pe riod or ab out 16 ns . in su ch an ex treme ca se th e di vided vc o wou ld ar rive 16 ns aft er the pd reference, an d wou ld al ways ar rive ou tside of th e 10 ns lo ck de tect wi ndow. in su ch a ca se th e lo ck detect circuit wou ld al ways re ad un locked, ev en th ough th e vc o mi ght be lo cked. wh en us ing th e 10 ns analog lock de tect wi ndow, wi th a 40 ns pd pe riod, th e of fset mu st al ways be le ss th an 25 % of th e ch arge pump setting, 20 % to al low fo r tol erances. he nce a 1 ma ch arge pu mp se tting ca n no t us e mo re th an 20 0 a offset with a 25 mh z pd an d an an alog lo ck de tect wi ndow. ch arge pu mp cu rrent, ch arge pu mp of fset, phase detector rate and lock detect window are related. 1.11.2 digital window lock detect setting reg 07h [6]=1 will r esult i n a v ariable l ength l ock d etect w indow b ased u pon a n i nternal d igital t imer. the timer pe riod is se t by th e nu mber of cy cles of th e in ternal ld cl ock as pr ogrammed by reg 07h [ 9 : 7 ] . the ld clock fre quency is ad justable by reg 07h [11:10]. the ld cl ock si gnal ca n be vi ewed vi a th e gp o test pins. refer 1.16 for details. 1.11.3 declaration of lock wincnt_max in reg 07h [2:0] defnes the nu mber of co nsecutive co unts of th e di vided vc o th at mu st la nd inside the lo ck de tect wi ndow to de clare lo ck. if fo r ex ample we se t wincnt_max = 2048, then th e vc o arrival would ha ve to oc cur in side th e wi ndow 20 48 ti mes in a ro w to be de clared lo cked, wh ich wou ld result in a lo ck de tect fl ag hi gh. a si ngle oc currence ou tside of th e wi ndow wi ll re sult in an ou t of lo ck, i. e. lock d etect f lag lo w. o nce lo w, th e l ock d etect f lag w ill s tay lo w u ntil th e wincnt_max = 2 048 c ondition is met again. the lock de tect fl ag st atus is al ways re adable in reg 12h [1] , if locked = 1. lo ck de tect st atus is al so output to the ld _sdo pi n if reg 0 fh [4:0]=1 . again, if locked, ld _sdo wi ll be hi gh. se tting reg 0 fh [6]=0 will display th e lo ck de tect fl ag on ld _sdo ex cept wh en a se rial po rt re ad is re quested, in wh ich ca se the pin reverts te mporarily to th e se rial da ta ou t pi n, an d re turns to th e lo ck de tect fl ag aft er th e re ad is completed. refer to 1.11.5 for timing of the lock detect information. plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 30 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz 1.11.4 phase offset & fractional linearity when operating in fra ctional mo de th e li nearity of th e ch arge pu mp an d ph ase de tector ar e mu ch mo re critical than in in teger mo de. th e ph ase de tector li nearity is de graded wh en op erating wi th ze ro ph ase offset. hence in fra ctional mo de it is ne cessary to of fset th e ph ase of th e pd re ference an d th e vc o at th e phase detector. in su ch a ca se, fo r ex ample wi th an of fset de lay, as sh own in figure 41 , the vco ar rival wi ll always occur aft er th e re ference. th e lo ck de tect ci rcuit wi ndow ma y ne ed to be ad justed to al low fo r th e delay being used. for details see section digital lock detect with digital window example . figure 41. lock detect window - fractional mode with offset 1.11.5 digital lock detect with digital window example typical digital lo ck de tect wi ndow wi dths ar e sh own in table 3 . lock detect wi ndows ty pically va ry 1 0% vs voltage and 25% over temperature (-40c to +85c). table 3. typical digital lock detect window ld timer speed reg07[11:10] digital lock detect window nominal value 25% (ns) fastest 0 0 6.5 8 11 17 29 53 100 195 01 7 8.9 12.8 21 36 68 130 255 10 1.7 9.2 13.3 22 38 72 138 272 slowest 1 1 7.6 10.2 15.4 26 47 88 172 338 ld t imer d ivide s etting reg07[9:7] 0 1 2 3 4 5 6 7 ld t imer divide v alue 0.5 1 2 4 8 16 32 64 as an example, if we op erate in fra ctional mo de at 2g hz wi th a 50 mhz pd , ch arge pu mp cu rrent ga in of 2ma and a do wn le akage of 40 0ua. th en ou r av erage of fset at th e pd wi ll be 0. 4ma/2ma = 0. 2 of th e pd p eriod o r a bout 4 ns ( 0.2 x 1 /50mhz). h owever, t he f ractional m odulation o f t he v co d ivider w ill r esult in time excursions of th e vc o di vider ou tput of +/ -4tvco fro m th is av erage va lue (2 ns in th is ex ample). hence, when in lo ck, th e di vided vc o wi ll ar rive at th e pd 4 +/ -2ns aft er th e di vided re ference. th e lo ck detect window al ways st arts on th e ar rival of th e fr st si gnal at th e pd , in th is ca se th e re ference. th e lo ck detect w indow m ust b e l onger t han 4 ns+2ns ( 6ns) a nd s horter t han t he p eriod o f t he p d, in t his e xample, 20ns. a perfect lock detect window would be midway between these two values, or 13ns. there is a al ways a go od so lution fo r th e lo ck de tect wi ndow fo r a gi ven op erating po int. th e us er plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 31 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz should u nderstand h owever t hat o ne s olution d oes n ot f t a ll o perating p oints. i f c harge p ump o ffset o r p d frequency are changed signifcantly then the lock detect window may need to be adjusted. figure 42. lock detect window example with 50 mhz pd and 3.9 ns vco offset 1.11.6 cycle slip prevention (csp) when changing vc o fre quency an d th e vc o is no t ye t lo cked to th e re ference, th e in stantaneous frequencies of th e two pd in puts ar e di fferent, an d th e ph ase di fference of th e two in puts at th e pd va ries rapidly over a ra nge mu ch gr eater th an 2 ra dians. si nce th e ga in of th e pd va ries li nearly wi th ph ase up to 2, th e ga in of a co nventional pd wi ll cy cle fro m hi gh ga in, wh en th e ph ase di fference ap proaches a multiple of 2 , to lo w ga in, wh en th e ph ase di fference is sl ightly la rger th an a mu ltiple of 0 ra dians. th e output current fro m th e ch arge pu mp wi ll cy cle fro m ma ximum to mi nimum ev en th ough th e vc o ha s no t yet reached its fnal frequency. the charge on th e lo op fl ter sm all ca p ma y ac tually di scharge sl ightly du ring th e lo w ga in po rtion of th e cycle. this ca n ma ke th e vc o fre quency ac tually re verse te mporarily du ring lo cking. th is ph enomena is known as cy cle sl ipping. cy cle sl ipping ca uses th e pu ll-in ra te du ring th e lo cking ph ase to va ry cy clically. cycle slipping in creases th e ti me to lo ck to a va lue gr eater th an th at pr edicted by no rmal sm all si gnal laplace analysis. the s ynthesizer p d f eatures a n abi lity t o r educe c ycle s lipping d uring a cquisition. th e c ycle s lip p reven - tion ( csp) f eature i ncreases t he p d g ain d uring l arge p hase e rrors. t he s pecifc p hase e rror t hat t riggers the momentary increase in pd gain is set via reg 0bh [8:7] 1.11.7 charge pump gain a simplifed di agram of th e ch arge pu mp is sh own in figure 43 . charge pump up an d do wn ga ins ar e se t by cp dn gain and cp up gain respectively ( reg 09h [6:0] and reg 09h [13:7]) . the current ga in of th e pump in amps/radian is equal to the gain setting of this register divided by 2. for example if bo th cp dn gain and cp up gain are set to 50d th e ou tput cu rrent of ea ch pu mp wi ll be 1 ma and the ph ase fre quency de tector ga in k p = 1 ma/2 ra dians, or 15 9 a/ rad. se e se ction 1.4 for more information. 1.11.8 charge pump phase offset - fractional mode in integer mo de, th e ph ase de tector op erates wi th ze ro of fset. th e di vided re ference si gnal an d th e di vided vco signal ar rive at th e ph ase de tector in puts at th e sa me ti me. in fra ctional mo de of op eration, ch arge pump linearity an d ul timately, ph ase no ise, is mu ch be tter if th e vc o an d re ference in puts ar e op erated with a phase of fset. a ph ase of fset is im plemented by ad ding a co nstant dc of fset cu rrent at th e ou tput of the charge pump. dc offset ma y be ad ded to th e up or dn sw itching pu mps us ing reg 09h [21] or reg 09h [22] . the plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 32 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz magnitude of th e of fset is co ntrolled by reg 09h [20:14], and ca n ra nge fro m 0 to 63 5 a in st eps of 5 a. down offset is hi ghly re commended in fra ctional mo de of op eration. in teger mo de of op eration wor ks be st with zero offset. as an example, a pd co mparison of f pd = 5 0 m hz ( 20 n s p eriod) w ith t he m ain p ump g ain s et a t 2 m a, a nd a down (dn) of fset of -3 85 a wou ld re present a ph ase of fset of ab out (- 385/2000)*360 = -6 9 de grees. this is equivalent to th e di vided vc o ar riving 3. 8 ns aft er th e re ference at th e pd in put. it is cr itical th at phase offset be used in fractional mode. normally, down offsets larger than 3 ns are typical. if the charge pu mp ga in is ch anged, fo r ex ample to co mpensate fo r ch anges in vc o se nsitivity, it is recommended to change the charge pump offset proportionally to maintain a constant phase offset. figure 43. charge pump gain & offset control 1.12 frequency tuning HMC833LP6GE vc o su bsystem al ways op erates in fu ndamental fre quency of op eration (1 500 mh z to 3000 mhz). th e hm c833lp6ge ge nerates fre quencies be low it s fu ndamental fre quency (2 5 mh z to 15 00 mhz) by tuning to th e ap propriate fu ndamental fre quency an d se lecting th e ap propriate ou tput di vider setting (divide by 2/ 4/6.../60/62) in vco_reg 0 2h b iases [5:0]. conversely th e HMC833LP6GE ge nerates frequencies gr eater th an it s fu ndamental fre quency (3 000 mh z to 60 00 mh z) by tu ning to th e ap propriate fundamental frequency and enabling the doubler mode ( vco_reg 03h [0] = 0 ). the HMC833LP6GE au tomatically co ntrols fre quency tu ning in th e fu ndamental ba nd of op eration, fo r more information see 1.2.1 vco auto-calibration (autocal) . to tune to fre quencies be low th e fu ndamental fre quency ra nge (< 1500 mh z) it is re quired to tu ne th e HMC833LP6GE to th e ap propriate fu ndamental fre quency, th en se lect th e ap propriate ou tput di vider setting (divide by 2/ 4/6.../60/62) in vco_reg 0 2h b iases [5:0]. similarly, to tu ne to fre quencies ab ove th e fundamental fre quency ra nge (> 30 00 mh z) it is re quired to tu ne th e HMC833LP6GE to th e ap propriate fundamental frequency, and then enable the doubler mode of operation ( vco_reg 03h [0] = 0 ). 1.12.1 integer mode the HMC833LP6GE is capable of operating in integer mode. for integer mode set the following registers a. disable the fractional modulator, reg 06h [11]= 0 b. bypass the modulator circuit, reg 06h [7]=1 in integer mo de th e vc o st ep si ze is fx ed to th at of th e pd fre quency, f pd . integer mode ty pically ha s 3 db lower phase no ise th an fra ctional mo de fo r a gi ven pd op erating fre quency. in teger mo de, ho wever, often requires a lo wer pd fre quency to me et st ep si ze re quirements. th e fra ctional mo de ad vantage is th at plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 33 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz higher pd fre quencies ca n be us ed, he nce lo wer ph ase no ise ca n of ten be re alized in fra ctional mo de. charge pump offset should be disabled in integer mode. 1.12.1.1 integer frequency tuning in integer mo de th e di gital ? mo dulator is sh ut of f an d th e n ( reg 0 3h ) divider may be pr ogrammed to an y integer value in th e ra nge 16 to 2 19 -1. to run in in teger mo de co nfgure reg 0 6h as d escribed, t hen p rogram the integer portion of the frequency as explained by (eq 13) , ignoring the fractional part. a. disable the fractional modulator, reg 06h [11] = 0 b. bypass the delta-sigma modulator reg 06h [7] = 1 c. to tune to fre quencies (< 1500 mh z), se lect th e ap propriate ou tput di vider va lue vco_reg 02 h biases [5:0]. d. to tune to frequencies (>3000 mhz), enable the doubler mode of operation ( vco_reg 03h [0] = 1). writing to vc o su bsystem re gisters ( vco_reg 02 h bi ases [5:0] and vco_reg 03 h [0] in this ca se ) is accomplished in directly thr ough pl l re gister 5 ( reg 05h ). more information on co mmunicating wi th th e vco subsystem through pll reg 05h is available in 1.19 vco serial port interface (spi) section. 1.12.2 fractional mode the HMC833LP6GE is placed in fractional mode by setting the following registers: a. enable the fractional modulator, reg 06h [11]=1 b. connect the delta sigma modulator in circuit, reg 06h [7]=0 1.12.2.1 fractional frequency tuning this is a generic ex ample, wi th th e go al of ex plaining ho w to pr ogram th e ou tput fre quency. ac tual va riables are dependant upon the reference in use. the HMC833LP6GE in fra ctional mo de ca n ac hieve fre quencies at fra ctional mu ltiples of th e re ference. the frequency of the HMC833LP6GE, f vco , is given by f vco = ( n int + n frac ) = f int + f frac f xtal r (eq 13) f out = f vco / k (eq 14) where: f out is t he o utput fr equency af ter a ny p otential d ividers o r d oublers. k is 0 .5 f or d oubler, 1 f or f undamental, o r k = 1 ,2,4,6,58,60,62 a ccording to t he vco subsystem type n int is t he i nteger d ivision r atio, reg 03h , an integer number between 20 and 5 2 4 , 2 8 4 n frac is t he fr actional p art, fr om 0 .0 to 0 .99999...,n frac = reg 04h /2 24 r is t he r eference p ath d ivision r atio, reg 02h f xtal is t he fr equency o f t he r eference o scillator i nput f pd is t he p d o perating fr equency, f xtal /r plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 34 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz as an example: f out 1402.5 mhz k 2 f vco 2,805 m hz f xtal = 5 0 m hz r = 1 f pd = 5 0 m hz n int = 5 6 n frac = 0 .1 reg 04h = round(0.1 x 2 24 ) = round(1677721.6) = 1677722 f vco = ( 56 + ) = 2 805 mhz + 1 .192 hz error 1677722 2 24 50e6 1 (eq 15) f out = = 1402 .5 mhz + 0 .596 hz error f vco 2 (eq 16) in this example th e ou tput fre quency of 14 02.5 mh z is ac hieved by pr ogramming th e 19 -bit bi nary va lue of 56d = 38h in to intg_reg in reg 0 3h , and the 24-bit bi nary va lue of 16 77722d = 19 999ah in to frac_reg in reg 0 4h . the 0.596 hz qu antization er ror ca n be el iminated us ing th e ex act fre quency mo de if re quired. in this example th e ou tput fu ndamental is di vided by 2. sp ecifc co ntrol of th e ou tput di vider is re quired. se e section 3.0 and description for more details. 1.12.2.2 exact frequency tuning due to quantization ef fects, th e ab solute fre quency pr ecision of a fra ctional pl l is no rmally li mited by the number of bi ts in th e fra ctional mo dulator. fo r ex ample, a 24 bi t fra ctional mo dulator ha s fre quency resolution se t by th e ph ase de tector (p d ) co mparison ra te di vided by 2 24 . t he v alue 2 24 in the denominator is sometimes re ferred to as th e mo dulus. hi ttite pl ls us e a fx ed mo dulus wh ich is a bi nary nu mber. in some types of fra ctional pl ls th e mo dulus is va riable, wh ich al lows ex act fre quency st eps to be ac hieved with decimal st ep si zes. un fortunately sm all st eps us ing sm all mo dulus va lues re sults in la rge sp urious outputs at mu ltiples of th e mo dulus pe riod (c hannel st ep si ze). fo r th is re ason hi ttite pl ls us e a la rge fxed modulus. no rmally, th e st ep si ze is se t by th e si ze of th e fx ed mo dulus. in th e ca se of a 50 mh z pd rate, a modulus of 2 24 would result in a 2. 98 hz st ep re solution, or 0. 0596 pp m. in so me ap plications it is necessary to have exact frequency steps, and even an error of 3 hz cannot be tol er ated. fractional pl ls ar e ab le to ge nerate ex act fre quencies (w ith ze ro fre quency er ror) if n ca n be exactly represented in bi nary (e g. n = 50 .0,50.5,50.25,50.75 et c.). un fortunately, so me co mmon frequencies ca nnot be ex actly re presented. fo r ex ample, n frac = 0.1 = 1/10 mu st be ap proximated as round((0.1 x 2 24 )/ 2 24 ) 0.100000024. at f pd = 50 mhz this tr anslates to 1. 2 hz er ror. hi ttites ex act fre quency mode addresses th is is sue, an d ca n el iminate qu antization er ror by pr ogramming th e ch annel st ep si ze to f pd /10 in reg 0ch to 10 (in this ex ample). mo re ge nerally, th is fe ature ca n be us ed wh enever th e de sired frequency, f vco , can be exactly re presented on a st ep pl an wh ere th ere ar e an in teger nu mber of st eps (<2 14 ) across in teger-n bo undaries. ma thematically, this si tuation is sa tisfed if : gcd gcd gcd 1 14 mod 0 where gcd( , ) 2 pd pd vcok vco f f f f f f and f ?? ?? ?? ?? ?? ?? ?? = = (eq 17) plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 35 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz where: gcd stands for greatest common divisor f n = maximum integer boundary frequency < f vco1 f pd = frequency of the phase detector and f vcok are the channel step frequencies where 0 < k < 2 24 -1, as shown in figure 44 . figure 44. exact frequency tuning some fractional pl ls ar e ab le to ac hieve th is by ad justing (s hortening) th e le ngth of th e ph ase ac cumulator (the denominator or th e mo dulus of th e de lta-sigma mo dulator) so th at th e de lta-sigma mo dulator ph ase accumulator re peats at an ex act pe riod re lated to th e in terval fre quency ( f vcok - f vco(k-1) ) in figure 44 . consequently, th e sh ortened ac cumulator re sults in mo re fre quent re peating pa tterns an d as a re sult of ten leads to spurious em issions at mu ltiples of th e re peating pa ttern pe riod, or at ha rmonic fre quencies of f vcok - f vco(k-1) . for example, in so me ap plications, th ese in tervals mi ght re present th e sp acing be tween radio channels, and the spurious would occur at multiples of the channel spacing. the hittite me thod on th e ot her ha nd is ab le to ge nerate ex act fre quencies be tween ad jacent in teger-n boundaries wh ile st ill us ing th e fu ll 24 bi t ph ase ac cumulator mo dulus, th us ac hieving ex act fre quency steps with a hi gh ph ase de tector co mparison ra te, wh ich al lows hi ttite pl ls to ma intain ex cellent ph ase noise and spurious performance in the exact frequency mode. 1.12.2.3.3 using hittite exact frequency mode if the constraint in (eq 17) is satisfed, hm c833lp6ge is ab le to ge nerate si gnals wi th ze ro fre quency er ror at the desired vc o fre quency. ex act fr equency mo de ma y be re -confgured fo r ea ch ta rget fre quency, or be set-up for a fxed f gcd which applies to all channels. 1.12.2.4.4 confguring exact frequency mode for a particular frequency 1. calculate an d pro gram th e int eger re gister set ting reg 03h = n int = foor( f vco /f pd ), where the foor function is th e ro unding do wn to th e ne arest in teger. th en th e in teger bo undary fre quency f n = n int ? f pd 2. calculate an d pr ogram th e ex act fre quency re gister va lue reg 0ch = f pd /f gcd , where f gcd = gcd( f vco , f pd ) 3. calculate an d pro gram th e fr actional re gister set ting reg 04h ( ) 24 2 ceil n vco frac pd ff n f ?? ?? ?? ?? ?? ? = = , where ceil is the ceiling function meaning round up to the nearest integer. example: to confgure the HMC833LP6GE for exact frequency mode at f vco = 2800.2 mhz where phase detector (pd) rate f pd = 61.44 mhz proceed as follows: plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 36 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz check (eq 17) to confrm that the exact frequency mode for this f vco is possible. ( ) gcd gcd 14 6 66 3 gcd 14 gcd( , ) 2 61.44 10 gcd 2800.2 10 ,61.44 10 120 10 3750 2 pd pd vco f f f f and f f ?? ?? ?? ?? = = => = since (eq 17) is satisfed, th e hm c833lp6ge ca n be co nfgured fo r ex act fre quency mo de at f vco = 2800.2 mhz as follows: 1. n int = reg 03h = 6 6 2800.2 10 45 2 61.44 10 vco pd f floor floor d dh f ?? ?? ?? ?? ?? ?? ?? ?? = = = 2. reg 0ch = ( ) ( ) 66 66 61.44 10 61.44 10 512 200 120000 gcd , gcd 2800.2 10 ,61.44 10 pd pd vco f dh ff = = = = 3. to program reg 04h , the closest in teger-n bo undary fre quency f n that is less th an th e desired vco fre quency f vco must be ca lculated. f n = f pd ? n int . using the cu rrent ex ample: ( ) ( ) 6 24 6 6 24 6 45 61.44 10 2764.8 . 2 2800.2 10 2764.8 10 2 then reg04h 9666560 938000 61.44 10 int n pd n vco pd n f f mhz ff ceil ceil d h f ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? = = = ? ? = = = = 1.12.2.5.5 hittite exact frequency channel mode if it is desirable to ha ve mu ltiple, eq ually sp aced, ex act fre quency ch annels th at fa ll wi thin the same in terval (i e. f n f vcok < f n+1 ) where f vcok is shown in figure 44 and 1 k 2 14 , it is possible to ma intain th e sa me in teger-n ( reg 03h ) and exact fre quency re gister ( reg 0ch ) settings and only update the fractional register ( reg 04h ) setting. the exact frequency channel mode is possible if (eq 17) is satisfed fo r at le ast two eq ually sp aced ad jacent fre quency ch annels, i. e. th e ch annel st ep size. to confgure th e hm c833lp6ge fo r ex act fr equency ch annel mo de, in itially an d on ly at th e be ginning, integer ( reg 03h ) and exact fre quency ( reg 0ch ) registers ne ed to be pr ogrammed fo r th e sm allest f vco frequency ( f vco1 in figure 44 ), as follows: 1. calculate an d pro gram th e int eger re gister set ting reg 03h = n int = foor( f vco1 /f pd ), where f vco1 is shown in figure 44 and corresponds to mi nimum ch annel vc o fre quency. th en th e lo wer in teger boundary frequency is given by f n = n int ? f pd . 2. calculate an d pr ogram th e ex act fre quency re gister va lue reg 0ch = f pd /f gcd, where f gcd = g cd(( f vcok+1 - f vcok ), f pd ) = greatest co mmon di visor of th e de sired eq uidistant ch annel spacing and the pd frequency (( f vcok+1 - f vcok ) and f pd ). then, to switch be tween va rious eq ually sp aced in tervals (c hannels) on ly th e fra ctional re gister ( reg 0 4h ) needs to be programmed to the desired vco channel frequency f vcok in the following manner: r e g 0 4 h = ( ) 24 2 ceil n vcok frac pd ff n f ?? ?? ?? ?? ?? ? = w h e r e f n = f o o r ( f vco1 /f pd ), and f vco1 , as shown in figure 44 , represents the smallest channel vco frequency that is greater than f n . example: to confgure the HMC833LP6GE for exact frequency mode for equally spaced intervals of 100 khz where frst channel (channel 1) = f vco1 = 2800.200 mhz and phase detector (pd) rate f pd = 61.44 mhz proceed as follows: first check th at th e ex act fre quency mo de fo r th is f vco1 = 2800.2 mh z (c hannel 1) and f vco2 = 2800.2 mhz + 100 khz = 2800.3 mhz (channel 2) is possible. plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 37 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz ( ) ( ) gcd1 gcd1 gcd 2 gcd 2 12 14 14 6 66 3 gcd1 14 6 6 63 gcd 2 14 gcd( , ) gcd( , ) 22 61.44 10 gcd 2800.2 10 ,61.44 10 120 10 3750 2 61.44 10 gcd 2800.3 10 ,61.44 10 20 10 3750 2 pd pd pd pd vco vco ff f f f and f and f f f and f f f ?? ?? ?? ?? ?? ?? ?? ?? = = = => = = => = if (eq 17) is satisfed fo r at le ast two of th e eq ually sp aced in terval (c hannel) fre quencies f vco1 ,f vco2 ,f vco3 ,... f vcon , as it is above, hi ttite ex act fr equency ch annel mo de is po ssible fo r al l de sired ch annel fre quencies, and can be confgured as follows: 1. reg 03h = 6 1 6 2800.2 10 45 2 61.44 10 vco pd f floor floor d dh f ?? ?? ?? ?? ?? ?? ?? ?? = = = 2. reg 0ch = ( ) ( ) ( ) 66 36 1 61.44 10 61.44 10 3072 00 20000 gcd 100 10 ,61.44 10 gcd , pd pd vcok vcok f dc h f ff + = = = = ? where ( f vcok+1 - f vcok ) is the desired channel spacing (100 khz in this example). 3. to program reg 04h the closest integer-n boundary frequency f n that is less than the smallest channel vco frequency f vco1 must be calculated. f n = foor( f vco1 /f pd ). using the current example: 6 6 6 2800.2 10 45 61.44 10 2764.8 61.44 10 n pd f f floor mhz ?? ?? ?? ?? = = = then reg 04h ( ) ( ) 24 1 1 24 6 6 6 2 for channel 1 where 2800.2 2 2800.2 10 2764.8 10 9666560 938000 61.44 10 n vco vco pd ff ceil f mhz f ceil d h ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ? = = ? = = = 4. to change from channel 1 ( f vco1 = 2800.2 mhz) to channel 2 ( f vco2 = 2800.3 mhz), only reg 04h needs to be programmed, as long as all of the desired exact frequencies f vcok ( figure 44 ) fall between the same integer-n boundaries ( f n < f vcok < f n+1 ). in that case reg 04h = ( ) 24 6 6 6 2 2800.3 10 2764.8 10 9693867 93 61.44 10 ceil d eaabh ?? ?? ?? ?? ?? ?? ? = = , and so on. 1.12.2.6 seed register & autoseed mode the start phase of th e fra ctional mo dulator di gital ph ase ac cumulator (d pa) ma y be se t to on e of fo ur po ssible default values vi a th e se ed re gister reg 0 6h [1:0] . if autoseed reg 0 6h [8] is s et, t hen t he h mc833lp6ge will automatically re load th e st art ph ase in to th e dp a ev ery ti me a ne w fra ctional fre quency is se lected. if autoseed is no t se t, th en th e hm c833lp6ge wi ll st art ne w fra ctional fre quencies wi th th e la st va lue left in the dp a fro m th e la st fre quency. he nce th e st art ph ase wi ll ef fectively be ra ndom. ce rtain ze ro or binary seed va lues ma y ca use sp urious en ergy co rrelation at sp ecifc fre quencies. co rrelated sp urs ar e advantageous on ly in ve ry sp ecial ca ses wh ere th e sp urious ar e kn own to be fa r ou t of ba nd an d ar e removed in th e lo op fl ter. fo r mo st ca ses a ra ndom, or no n ze ro, no n-binary st art se ed is re commended. further, since th e au toseed al ways st arts th e ac cumulators at th e sa me pl ace, pe rformance is re peatable if autoseed is used. reg 06h [1:0]=2 is recommended. plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 38 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz 1.13 soft reset & power-on reset the h mc833lp6ge f eatures a h ardware p ower o n r eset ( por). a ll c hip r egisters w ill b e r eset t o d efault states approximately 250 s after power up. the pll subsystem sp i re gisters ma y al so be so ft re set by an sp i wr ite to re gister rst_swrst ( reg 00h ) . note that the so ft re set do es no t cl ear th e sp i mo de of op eration re ferred to in se ction 1.17. 2 . the soft reset is applied by wr iting reg 00h [5]=1. t he r eset i s a o ne t ime e vent t hat o ccurs i mmediately. t he r eset b it does not have to be re turned to 0 aft er a re set. it sh ould be no ted th at th e vc o su bsystem is no t aff ected by the pll soft reset. the vco subsystem registers can only be reset by removing the power supply. note: if external power supplies or regulators have rise times slower than 250 s, then it is advised to write to the spi reset register ( reg 00h [5]=1) immediately after power up, before any other spi activity. this will ensure starting from a known state. 1.14 power down mode note t hat t he v co s ubsystem i s n ot a ffected b y t he c en o r s oft r eset. h ence d evice p ower d own i s a t wo step process. fi rst po wer do wn th e vc o by wr iting 0 to vc o re gister 1 vi a reg 0 5h and t hen p ower d own the p ll b y p ulling c en p in 1 7 l ow ( assuming n o s pi o verrides ( reg 01h [0]=1)). this wi ll re sult in al l an alog functions and in ternal cl ocks di sabled. cu rrent co nsumption wi ll ty pically dr op be low 10 a in po wer do wn state. the serial port will still respond to normal communication in power down mode. it is possible to ig nore th e ce n pi n, by cl earing rst_chipen_pin_select ( reg 01h [0]=0) . control of po wer down mode then comes from the serial port register rst_chipen_from_spi, reg 01h [1] . it is also possible to leave various blocks on when in power down (see reg 01h ) , including: a. internal bias reference sources reg 01h [2] b. pd block reg 01h [3] c. cp block reg 01h [4] d. reference path buffer reg 01h [5] e. vco path buffer reg 01h [6] f. digital i/o test pads reg 01h [7] to turn off th e vc o rf bu ffer bu t le ave th e vc o ru nning an d th e pl l lo cked wr ite reg 05h =d88h. to re-enable the rf bu ffer wr ite reg 0 5h =f88h. prior to pr ogramming a ne w fre quency se t reg 0 5h [6:0]=0. 1.15 chip identifcation pll subsystem ve rsion in formation ma y be re ad by re ading th e co ntent of re ad on ly re gister, ch ip_id in reg 00h . it is not possible to read the vco subsystem version. 1.16 general purpose output (gpo) pin the pll shares th e ld _sdo (l ock-detect/serial da ta ou t) pi n to pe rform va rious fu nctions. wh ile th e pi n is most commonly us ed to re ad ba ck re gisters fro m ch ip vi a th e sp i, it is al so ca pable of ex porting a va riety of interesting si gnals an d re al ti me te st wa veforms (i ncluding lo ck de tect). it is dr iven by a tr i-state cm os driver with ~2 00 ro ut. it ha s lo gic as sociated wi th it to dy namically se lect wh ether th e dr iver is en abled, and to decide which data to export from the chip. in its default co nfguration, aft er po wer-on-reset, th e ou tput dr iver is di sabled, an d on ly dr ives du ring appropriately a ddressed s pi r eads. t his a llows i t t o s hare t he o utput w ith o ther d evices o n t he s ame b us. depending on the spi mode, the read section of spi cycle is recognized differently hmc spi mo de: th e dr iver is en abled du ring th e la st 24 bi ts of sp i re ad cy cle (n ot du ring wr ite cycles). open spi mo de: th e dr iver is en abled if th e ch ip is ad dressed - ie . th e la st 3 bi ts of sp i cy cle = plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 39 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz 000b before the rising edge of sen (note a). to monitor an y of th e gp o si gnals, in cluding lo ck de tect, se t reg 0fh [7] = 1 to ke ep th e sd o dr iver always on. th is sto ps th e ld o dr iver fro m tr i-stating an d me ans th at th e sd o li ne ca nnot be sh ared wi th other devices. the chip will na turally sw itch aw ay fro m th e gp o da ta an d ex port th e sd o du ring an sp i re ad (n ote b) . to prevent this au tomatic da ta se lection, an d al ways se lect th e gp o si gnal, se t p revent au tomux of sd o ( reg 0 fh [6] = 1). the ph ase no ise pe rformance at th is ou tput is po or an d un characterized. al so, th e gp o output should no t be to ggling du ring no rmal ope ration. oth erwise the spe ctral per formance may de grade. note that there ar e ad ditional co ntrols av ailable, wh ich ma y be he lpful if sh aring th e bu s wi th ot her de vices: ? to allow the dr iver to be ac tive (s ubject to th e co nditions ab ove) ev en wh en th e ch ip is di sabled - se t reg 01h [7] = 0. ? to disable the driver completely, set reg 08h [5] = 0 (it takes precedence over all else). ? to disable ei ther th e pu ll-up or pu ll-down se ctions of th e dr iver, reg 0fh [8] = 1 or reg 0fh [9] = 1 respectively. note a: if sen rises before sck has clocked in an invalid (non-zero) chip -address, the HMC833LP6GE will start to drive the bus. note b: in open mode, the active portion of the read is defned between the 1 st sck rising edge after sen, to the next rising edge of sen. example scenarios: ? drive sdo during reads, tri-state otherwise (to allow bus-sharing) ? no action required. ? drive sdo during reads, lock detect otherwise ? set gpo select reg 0fh [4:0] = 00001 (which is default) ? set prevent gpo driver disable ( reg 0fh [7] = 1) ? always drive lock detect ? set prevent automux of sdo reg 0fh [6] = 1 ? set gpo select reg 0fh [4:0]= 00001 (which is default) ? set prevent gpo driver disable ( reg 0fh [7] = 1)) the signals available on the gpo are selected by changing gpo select, reg 0fh [4:0]. 1.17 serial port 1.17.1 serial port modes of operation the HMC833LP6GE serial port interface can operate in two different modes of operation. a. hmcspi hmc mode (hmc legacy mode) - single slave per hmcspi bus b. hmcspi open mode - up to 8 slaves per hmcspi bus. both modes su pport 5- bits of re gister ad dress sp ace. hm c mo de ca n su pport up to 6 bi ts of re gister address. register 0 ha s a de dicated fu nction in ea ch mo de. op en mo de al lows wi der co mpatibility wi th ot her manufacturers spi protocols. plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 40 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz table 4. register 0 comparison - single vs multi-user modes single user hmc mode multi-user open mode read chip id 24-bits chip id 24-bits write soft reset, general strobes read address [4:0] soft reset [5] general strobes [23:6] 1.17. 2 hmcspi protocol decision after power-on reset on power up both types of modes are active and listening. a decision to se lect th e de sired sp i pr otocol is ma de on th e fr st oc currence of se n or sc lk fo llowing a hard reset, after which the protocol is fxed and only changeable by cycling the power off and on. a. if a rising edge on sen is detected frst hmc mode is selected. b. if a rising edge on sclk is detected frst open mode is selected. 1.17.3 serial port hmc mode - single pll hmc mode (l egacy mo de) se rial po rt op eration ca n on ly ad dress an d ta lk to a si ngle pl l, an d is co mpatible with most hittite plls and plls with integrated vcos. the hmc mo de pr otocol, sh own in fg ures figure 45 and figure 46 , is designed fo r a 4 wi re in terface wi th a fxed protocol featuring a. 1 read/write bit b. 6 address bits c. 24 data bits d. 3 wire for write only, 4 wire for read/write capability 1.17.3.1 hmc mode - serial port write operation avdd = dvdd = 3v 10%, agnd = dgnd = 0v table 5. spi hmc mode - write timing characteristics parameter conditions min. typ. max units t 1 sen to sclk setup time 8 ns t 2 sdi to sclk setup time 3 ns t 3 sclk to sdi hold time 3 ns t 4 sen low dur ation 20 ns t 5 sck to sen fall 10 ns max serial port clock speed 50 mhz a typical hmc mode write cycle is shown in figure 45 . a. the master (h ost) bo th as serts se n (s erial po rt en able) an d cl ears sd i to in dicate a wr ite cy cle, followed b y a r ising e dge o f s ck. b. the slave (s ynthesizer) re ads sd i on th e 1s t ri sing ed ge of sc k aft er se n. sd i lo w in di ca tes a wr ite cycle (/wr). c. host places th e si x ad dress bi ts on th e ne xt si x fa lling ed ges of sc k, ms b fr st. d. slave sh ifts th e ad dress bi ts in th e ne xt si x ri sing ed ges of sc k (2 -7). e. host places th e 24 da ta bi ts on th e ne xt 24 fa lling ed ges of sc k, ms b fr st. f. slave sh ifts th e da ta bi ts on th e ne xt 24 ri sing ed ges of sc k (8 -31). g. the data is re gistered in to th e ch ip on th e 32 nd ri sing ed ge of sc k. h. sen is cl eared aft er a mi nimum de lay of t 5 . t his c ompletes t he w rite c ycle. plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 41 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz figure 45. hmc mode - serial port timing diagram - write 1.17.3 . 2 hmc mode - serial port read operation a typical hmc mode read cycle is shown in figure 46 . a. the master (h ost) as serts bo th se n (s erial po rt en able) an d sd i to in dicate a re ad cy cle, fo llowed by a r ising e dge s clk. n ote: t he lo ck d etect ( ld) f unction i s u sually m ultiplexed o nto t he ld _sdo pin. it is suggested th at ld on ly be co nsidered va lid wh en se n is lo w. in fa ct ld wi ll no t tog gle un til the frst active da ta bi t tog gles on ld _sdo, an d wi ll be re stored im mediately aft er th e tr ailing ed ge of the lsb of serial data out as shown in figure 46 . b. the slave (h mc833lp6ge) re ads sd i on th e 1s t ri sing ed ge of sc lk aft er se n. sd i hi gh in itiates the read cycle (rd) c. host places the six address bits on the next six falling edges of sclk, msb frst. d. slave registers the address bits on the next six rising edges of sclk (2-7). e. slave switches fro m lo ck de tect an d pl aces th e re quested 24 da ta bi ts on sd _ldo on th e ne xt 24 rising edges of sck (8-31), msb frst . f. host registers the data bits on the next 24 falling edges of sck (8-31). g. slave restores lock detect on the 32nd rising edge of sck. h. de-assertion of sen completes the cycle table 6. spi hmc mode - read timing characteristics parameter conditions min. typ. max units t 1 sen to sclk setup time 8 ns t 2 sdi to sclk setup time 3 ns t 3 sclk to sdi hold time 3 ns t 4 sen low dur ation 20 ns t 5 sclk to sdo delay 8.2ns+0.2 ns/pf ns t 6 recovery time 10 ns plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 42 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz figure 46. hmc mode - serial port timing diagram - read 1.17.4 serial port open mode the serial port open mode, shown in figure 47 and figure 48 , features: a. compatibility with general serial port protocols that use shift and strobe approach to communication b. compatible with hittite pll with integrated vco solutions, useful to address multiple chips of various types from a single serial port bus. the open mode protocol has the following general features: a. 3-bit chip address , can address up to 8 devices connected to the serial bus b. wide compatibility with multiple protocols from multiple vendors c. simultaneous write/read during the spi cycle d. 5-bit address space e. 3 wire for write only capability, 4 wire for read/write capability hittite plls wi th in tegrated vc os su pport op en mo de. so me le gacy pl l an d mi crowave pl ls wi th integrated vcos only support hmc mode. consult the relevant data sheets for details. typical serial port operation can be run with sclk at speeds up to 50 mhz. 1.17.4.1 open mode - serial port write operation avdd = dvdd = 3v 10%, agnd = dgnd = 0v table 7. spi open mode - write timing characteristics parameter conditions min. typ. max units t 1 sdi setup time to sclk rising edge 3 ns t 2 sclk rising edge to sdi hold time 3 ns t 3 sen low dur ation 10 ns t 4 sen high duration 10 ns t 5 sclk 32 rising edge to sen rising edge 10 ns t 6 recovery time 20 ns max serial port clock speed 50 mhz plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 43 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz a typical write cycle is shown in figure 47 . a. the master (h ost) pl aces 24 -bit da ta, d2 3:d0, ms b fr st, on sd i on th e fr st 24 fa lling ed ges of sc lk. b. the slave (HMC833LP6GE) shifts in data on sdi on the frst 24 rising edges of sclk c. master pl aces 5- bit re gister ad dress to be wr itten to, r4 :r0, ms b fr st, on th e ne xt 5 fa lling ed ges of sc lk (25-29) d. slave shifts the register bits on the next 5 rising edges of sclk (25-29). e. master pl aces 3- bit ch ip ad dress, a2 :a0, ms b fr st, on th e ne xt 3 fa lling ed ges of sc lk (3 0-32). hi ttite reserves chip address a2:a0 = 000 for all rf pll with integrated vcos. f. slave shifts the chip address bits on the next 3 rising edges of sclk (30-32). g. master asserts sen after the 32nd rising edge of sclk. h. slave registers the sdi data on the rising edge of sen. figure 47. open mode - serial port timing diagram - write 1.17.4 . 2 open mode - serial port read operation a typical read cycle is shown in figure 48 . in general, in op en mo de th e ld _sdo li ne is al ways ac tive du ring th e wr ite cy cle. du ring an y op en mode spi cy cle ld _sdo wi ll co ntain th e da ta fro m th e cu rrent ad dress wr itten in re g0h[4:0]. if re g0h[4:0] is not changed th en th e sa me da ta wi ll al ways be pr esent on ld _sdo wh en an op en mo de cy cle is in progress. if it is de sired to re ad fro m a sp ecifc ad dress, it is ne cessary in th e fr st sp i cy cle to wr ite th e desired address to reg0h[4:0], then in the next spi cycle the desired data will be available on ld_sdo. an example of the open mode two cycle procedure to read from any random address is as follows: a. the master (h ost), on th e fr st 24 fa lling e dges of sc lk pl aces 24 -bit da ta, d2 3:d0, ms b fr st, on sd i as shown in figure 48 . d23:d5 should be se t to ze ro. d4 :d0 = ad dress of th e re gister to be re ad on the next cycle. b. the slave (HMC833LP6GE) shifts in data on sdi on the frst 24 rising edges of sclk c. master pl aces 5- bit re gister ad dress , r4 :r0, (t he re ad ad dress re gister), ms b fr st, on th e ne xt 5 falling edges of sclk (25-29). r4:r0=00000. d. slave shifts the register bits on the next 5 rising edges of sclk (25-29). e. master pl aces 3- bit ch ip ad dress, a2 :a0, ms b fr st, on th e ne xt 3 fa lling ed ges of sc lk (3 0-32)..chip address is always 000 for rf pll with integrated vcos. f. slave shifts the chip address bits on the next 3 rising edges of sclk (30-32). g. master asserts sen after the 32nd rising edge of sclk. plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 44 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz h. slave registers the sdi data on the rising edge of sen. i. master clears sen to complete the the address transfer of the two part read cycle. j. if one does no t wi sh to wr ite da ta to th e ch ip at th e sa me ti me as we do th e se cond cy cle , th en it is recommended to si mply re write th e sa me co ntents on sd i to re gister ze ro on th e re ad ba ck pa rt of the cycle. k. master places the same sdi data as the previous cycle on the next 32 falling edges of sclk. l. slave (HMC833LP6GE) shifts the sdi data on the next 32 rising edges of sclk. m. slave places th e de sired re ad da ta (i e. da ta fro m th e ad dress sp ecifed in reg 00h [4:0] of the fr st cycle) on ld _sdo wh ich au tomatically sw itches to sd o mo de fro m ld mo de, di sabling th e ld output. n. master as serts se n aft er th e 32 nd ri sing ed ge of sc k to co mplete th e cy cle an d re vert ba ck to lo ck detect on ld_sdo. table 8. spi open mode - read timing characteristics parameter conditions min. typ. max units t 1 sdi setup time to sclk rising edge 3 ns t 2 sclk rising edge to sdi hold time 3 ns t 3 sen low dur ation 10 ns t 4 sen high duration 10 ns t 5 sclk rising edge to sdo time 8.2ns+0.2ns/pf ns t 6 recovery time 10 ns t 7 sck 32 rising edge to sen rising edge 10 ns plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 45 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz 1.17.4 .3 hmcspi open mode read operation - 2 cycles figure 48. serial port timing diagram - read for more information on using the gpo pin while in spi open mode please see section 1.16 . 1.18 confguration at start-up to confgure the pll after power up, follow the instructions below: 1. confgure the reference divider (write to reg 02h ), if required. 2. confgure the delta-sigma modulator (write to reg 06h ). plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 46 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz ? confguration in volves se lecting th e mo de of th e de lta-sigma mo dulator (m ode a or mo de b) , selection of th e de lta-sigma mo dulator se ed va lue, an d co nfguration of th e de lta-sigma mo dulator clock scheme. it is re commended to us e th e va lues fo und in th e hi ttite pl l ev aluation bo ard control software register fles. 3. confgure the charge pump current and charge pump offset current (write to reg 09h ) 4. confgure th e vc o su bsystem (w rite to reg 05h , for more in formation se e se ction 1.19 , and 3.0 vco subsystem re gister ma p . detailed wr ites to th e vc o su bsystem vi a pl l reg 05h at start-up are av ailable i n t he r egister s etting f iles f ound i n t he h ittite p ll e valuation s oftware r eceived w ith a product evaluation kit or downloaded from www.hittite.com . 5. program the frequency of operation ? program the integer part (write to reg 03h ) ? program the fractional part (write to reg 04h ) 6. confgure th e vc o ou tput di vider/doubler, if ne eded in th e vc o su bsystem vi a pl l reg 05h . once the hm c833lp6ge is co nfgured aft er st artup, in mo st ca ses th e us er on ly ne eds to ch ange frequencies by wr iting to reg 0 3h integer register, reg 0 4h fractional re gister, an d reg 0 5h to change th e vco output di vider or do ubler se tting if ne eded, an d po ssibly ad just th e ch arge pu mp se ttings by wr iting to reg 09h . for detailed an d mo st up -to-date st art-up co nfguration pl ease re fer to th e ap propriate re gister se tting files found in th e hi ttite pl l ev aluation so ftware re ceived wi th a pr oduct ev aluation ki t or do wnloaded from www.hittite.com . 1.19 vco serial port interface (spi) the HMC833LP6GE co mmunicates wi th th e in ternal vc o su bsystem vi a an in ternal 16 bi t vc o se rial port, (e.g. se e figure 29 ). the internal se rial po rt is us ed to co ntrol th e st ep tu ned vc o an d ot her vc o subsystem functions, such as rf output divider / doubler control and rf buffer enable. note that the in ternal vc o su bsystem sp i (v spi) ru ns at th e ra te of th e au tocal fs m cl ock, t fsm , (section 1. 2.1 ) where the fs m cl ock fre quency ca nnot be gr eater th an 50 mh z. th e vs pi cl ock ra te is se t by reg 0ah [14:13]. writes to the vc os co ntrol re gisters ar e ha ndled in directly, vi a wr ites to reg 0 5h of the pll. a wr ite to pl l reg 05h causes the pl l su bsystem to fo rward th e pa cket, ms b fr st, ac ross it s in ternal se rial li nk to th e vco subsystem, where it is interpreted. the vco se rial po rt ha s th e ca pability to co mmunicate wi th mu ltiple su bsystems in side th e ic . fo r th is reason each subsystem has a subsystem id, reg 05h [2:0]. each subsystem ha s mu ltiple re gisters to co ntrol th e fu nctions in ternal to th e su bsystem, wh ich ma y be different from on e su bsystem to th e ne xt. he nce ea ch su bsystem ha s in ternal re gister ad dresses bi ts ( reg 05h [6:3]) finally the da ta re quired to co nfgure ea ch re gister wi thin th e vc o su bsystem is co ntained in reg 0 5h [15:7]. 1.19.1 vspi use of reg05h the packet da ta wr itten in to, reg 05h is sub-parsed by lo gic at th e vc o su bsystem in to th e fo llowing 3 felds: 1. [2:0] - 3 bits - vco_id, target subsystem address = 000b. 2. [6:3] - 4 bits - vco_regaddr, the internal register address inside the vco subsystem. 3. [15:7] - 9- bits- vco_data, data feld to write into the vco register. for example, to wr ite 0_ 1111_1110 in to re gister 2 of th e vc o su bsystem (v co_id = 0 00b), an d se t th e plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 47 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz vco output di vider to di vide by 62 , th e fo llowing ne eds to be wr itten to reg 0 5h =0 _1111_1110, 0 0 10, 0 0 0 b. during autocal, th e au tocal co ntroller on ly up dates th e da ta fe ld of reg 0 5h . the vco su bsystem re gister address ( reg 05h [6:3]) must be set to 0000 for the autocal data to be sent to the correct address. vco subsystem id an d re gister ad dress ar e no t mo difed by th e au tocal st ate ma chine. he nce, if a manual access is do ne to a vc o su bsystem re gister th e us er mu st re set th e re gister ad dress to ze ro before a change of frequency which will re-run autocal. since every wr ite to reg 05h will result in a tr ansfer of da ta to th e vc o su bsystem, if th e vc o subsystem ne eds to be re set ma nually, it is im portant to ma ke su re th at th e vc o sw itch se ttings ar e not changed. he nce th e sw itch se ttings in reg 10h [7:0] need to be re ad fr st, an d th en re written to reg 05h [15:8]. in summary, frst read reg 10h , then write to reg 05h as follows: reg 10h [7:0] = vv x yyyyy reg 05h = vv x yyyyy 0 0000 iii reg 05h [2:0] = iii, subsystem id, 3 bits (000) reg 05h [6:3] = 0000, subsystem register address reg 05h [7] = 0 , calibration tune voltage off reg 05h [12:8] = yyyyy, vco caps reg 05h [13] = x, dont care reg 05h [15:14] = vv, vco select plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 48 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz 2.0 pll register map 2.1 reg 00h id register (read only) bit type name width default description [23:0] ro chip_id 24 a7975 HMC833LP6GE chip id 2.2 reg 00h open mode read address/rst strobe register (write only) bit type name width default description [4:0] wo read address 5 - (write only) read address for next cycle - open mode only [5] wo soft reset 1 - soft reset - both spi modes reset (set to 0 for proper operation) [23:6] wo not defned 18 - not defned (set to 0 for proper operation) 2.3 reg 01h rst register (default 000002 h) bit type name width default description [0] r/w rst_chipen_pin_select 1 0 1 = take pll enable via cen pin, see power down mode description 0 = take pll enable via spi (rst_chipen_from_spi) reg01[1] [1] r/w rst_chipen_from_spi 1 1 spis pll enable bit [2] r/w keep_bias_on 1 0 when pll is disabled, keeps internal bias generators on, ignores chip enable control. [3] r/w keep_pd_on 1 0 when pll is disabled, keeps pd circuit on, ignores chip enable control [4] r/w ke e p_ cp_ o n 1 0 when pll is disabled, keeps charge pump on, ignores chip enable control [5] r/w keep_ref_buf_on 1 0 when pll is disabled, keeps reference buffer block on, ignores chip enable control [6] r/w keep_vco_on 1 0 when pll is disabled, keeps vco divider buffer on, ignores chip enable control [7] r/w keep_gpo_driver_on 1 0 when pll is disabled, keeps gpo output driver on, ignores chip enable control [8] r/w reserved 1 0 reserved [9] r/w reserved 1 0 reserved 2.4 reg 02h refdiv register (default 000001 h) bit type name width default description [13:0] r/w rdiv 14 1 reference divider r value (eq 13) ) divider use also requires refbufen reg08[3]=1and divider min 1d max 16383d plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 49 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz 2.5 reg 03h frequency register - integer part (default 00001 9h) bit type name width default description [18:0] r/w intg 19 25d vco divider integer part, used in all modes, see (eq 13) fractional mo de min 20d max 2 19 -4 = 7fffch = 524,284d integer mode min 16d max 2 19 -1 = 7ffffh = 524,287d 2.6 reg 04h frequency register - fractional part (default 000000h ) bit type name width default description [23:0] r/w frac 24 0 vco divider fractional part (24-bit unsigned) see fractional frequency tuning used in fractional mode only (n frac = reg 04h /2 24 min 0d max 2 24 -1 2.7 reg 05h vco spi register (default 000000h ) bit type name width default description [2:0] r/w vco subsystem_id, 3 0 internal vco subsystem id [6:3] r/w vco subsystem register address 4 0 for interfacing with the vco please see section 1.19 . [15:7] r/w vco subsystem data 9 0 note: reg05h is a sp ecial re gister us ed fo r in direct ad dressing of th e vc o su bsystem. wr ites to re g05h ar e automatically forwarded to the vco subsystem by the vco spi state machine controller. reg05h is a re ad-write re gister. ho wever, re g05h on ly ho lds th e co ntents of th e la st tr ansfer to th e vc o su bsystem. hence it is no t po ssible to re ad th e fu ll co ntents of th e vc o su bsystem. on ly th e co ntent of th e la st tr ansfer to th e vco subsystem can be read. please take note special considerations for autocal related to reg05h plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 50 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz 2.8 reg 06h sd cfg register (default 200b4ah) bit type name width default description [1:0] r/w seed 2 2 selects the seed in fractional mode 00: 0 seed 01: lsb seed 02: b29d08h seed 03: 50f1cdh seed note; writes to this register are stored in the HMC833LP6GE and are only loaded into the modulator when a frequency change is executed and if autoseed reg06h[8] =1 [3:2] r/w order 2 2 select the modulator type 0: 1st order 1: 2nd order 2: mode b recommended 3: mode a [6:4] r/w reserved 3 4 program to 4d [7] r/w frac_bypass 1 0 0: use modulator, required for fractional mode, 1: bypass modulator, required for integer mode note: in bypass fractional modulator output is ignored, but fractional modulator continues to be clocked if frac_ rstb =1, can be used to test the isolation of the digital fractional modulator from the vco output in integer mode [8] r/w autoseed 1 1 1: loads the seed whenever the frac register is written 0: when frac register write changes frequency, modulator starts with previous contents [9] r/w clkrq_refdiv_sel 1 1 selects the modulator clock source- for test only 1: vco divider clock (recommended for normal operation) 0: ref divider clock ignored if bits [10] or [21] are set [10] r/w sd modulator clk select 1 0 program 1 [11] r/w sd enable 1 1 0: disable frac core, use for integer mode or integer mode with csp 1: enable frac core, required for fractional mode, or integer isolation testing this register controls whether autocal starts on an integer or a fractional write [12] r/w reserved 1 0 [13] r/w reserved 1 0 [15:14] r/w reserved 2 0 [17:16] r/w reserved 2 0 program to 3d [18] r/w bist enable 1 0 enable built in self test [20:19] r/w rdiv bist cycles 2 0 rdiv bist cycles 00: 1032 01: 2047 10: 3071 11: 4095 [21] r/w auto_clock_confg 1 1 program 0 [22] r/w reserved 1 0 plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 51 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz 2.9 reg 07h lock detect register (default 00014dh) bit type name width default description [2:0] r/w lkd_wincnt_max 3 5d lock detect window sets the number of consecutive counts of divided vco that must land inside the lock detect window to declare lock 0: 5 1: 32 2: 96 3: 256 4: 512 5: 2048 6: 8192 7: 65535 [3] r/w enable internal lock detect 1 1 see section 1.16 [5:4] r/w reserved 2 0 reserved [6] r/w lock detect window type 1 1 lock detection window timer selection 1: digital programmable timer 0: analog one shot, nominal 10 ns window [9:7] r/w ld digital window duration 3 2 0 lock detection - digital window duration 0: 1/2 cycle 1: 1 cycle 2: 2 cycles 3: 4 cycles 4: 8 cycles 5: 16 cycles 6: 32 cycles 7: 64 cycles [11:10] r/w ld digital timer freq control 2 0 lock detect digital timer frequency control 00 fastest 11 slowest [12] r/w ld timer test mode 1 0 1: force timer clock on continuously - for test only 0: normal timer operation - one shot [13] r/w auto relock - one try 1 0 1: attempts to relock if lock detect fails for any reason only tries once. plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 52 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz 2.10 reg 08h analog en register (default c1beffh) bit type name width default description [0] r/w bias_en 1 1 enables main chip bias reference. program 1 [1] r/w cp_en 1 1 charge pump enable. program 1 [2] r/w pd_en 1 1 pd enable. program 1 [3] r/w refbuf_en 1 1 reference path buffer enable. program 1 [4] r/w vcobuf_en 1 1 vco path rf buffer enable. program 1 [5] r/w gpo_pad_en 1 1 0 - pin ld_sdo disabled 1 - and regfh[7]=1 , pin ld_sdo is always on required for use of gpo port 1 - and regfh[7]=0 spi ldo_spi is off if unmatched chip address is seen on the spi, allowing a shared spi with other compatible pa rts [6] r/w reserved 1 1 program 1 [7] r/w vco_div_clk_to_dig_en 1 1 program 1 [8] r/w reserved 1 0 program 0 [9] r/w prescaler clock enable 1 1 program 1 [10] r/w vco buffer and prescaler bias enable 1 1 program 1 [11] r/w charge pump internal opamp enable 1 1 program 1 [14:12] r/w reserved 3 011 program 011 [17:15] r/w reserved 3 011 program 011 [18] r/w spare 1 0 dont care [19] r/w reserved 1 0 program 0 [20] r/w reserved 1 0 program 0 [21] r/w high frequency reference 1 0 program 1 for ref in >= 200 mhz, 0<200 mhz [22] r/w reserved 1 1 dont care [23] r/w reserved 1 1 dont care plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 53 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz 2 .11 reg 09h charge pump register (default 403264h) bit type name width default description [6:0] r/w cp dn gain 7 100d 64h charge pump dn gain control 20 astep affects fractional phase noise and lock detect settings 0d = 0 a 1d = 20 a 2d = 40 a ... 127d = 2.54ma [13:7] r/w cp up gain 7 100d 64h charge pump up gain control 20 a per step affects fractional phase noise and lock detect settings 0d = 0 a 1d = 20 a 2d = 40 a ... 127d = 2.54ma [20:14] r/w offset magnitude 7 0 charge pump offset control 5 a/step affects fractional phase noise and lock detect settings 0d = 0 a 1d = 5 a 2d = 10 a ... 127d = 635 a [21] r/w offset up enable 1 0 recommended setting = 0 [22] r/w offset dn enable 1 1 recommended setting = 1 in fractional mode, 0 otherwise [23] r/w hikcp 1 0 hikcp high current charge pump plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 54 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz 2.12 reg 0ah vco autocal confguration register (default 002205h) bit type name width default description [2:0] r/w vtune resolution 3 5 r divider cycles 0 - 1 1 - 2 2 - 4 3 - 8 4 - 32 5 - 64 6 - 128 typical confguration 7-256 [5:3] r/w vco curve adjustment 3 0 program 000 vco curve adjustment vs temp for autocal 0 - disabled 1 : + 1 curve 2: +2 curves 3: +3 curves 4: -4 curves 5: -3 curves 6: -2 curves 7: -1 curve [7:6] r/w wait state set up 2 0 program 01 wait state setup 100 t fsm see section 1.2.4 t mmt = 1 measurement cycle of autocal 0: wait only at startup 1: wait on startup and after frst t mmt cycle 2: wait on startup and after frst two t mmt cycles 3: wait on startup and after frst three t mmt cycles [9:8] r/w num of sar bits in vco 2 2 number of sar bits in vco 0: 8 recommended 1: 7 do not use 2: 6 do not use 3: 5 do not use [10] r/w force curve 1 0 program 0 [11] r/w bypass vco tuning 1 0 program 0 for normal operation using auto calibration [12] r/w no vspi trigger 1 0 program 0 for normal operation. if 1, serial transfers to vco sub-system (via reg 05h ) are disabled [14:13] r/w fsm/vspi clock select 2 1 set the autocal fsm and vspi clock (50 mhz maximum) 0: input crystal reference 1: input crystal reference/4 2: input crystal reference/16 3: input crystal reference/32 [15] r/w xtal falling edge for fsm 1 0 program 0 for normal operation. program 1 only for bist use [16] r/w force rdivider bypass 1 0 program 0 plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 55 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz 2.13 reg 0bh pd register (default f8061h) bit type name width default description [2:0] r/w pd_del_sel 3 1 sets pd reset path delay (recommended setting 001) [3] r/w short pd inputs 1 0 program 0 for normal operation. shorts the inputs of the phase frequency detector - test only [4] r/w pd_phase_sel 1 0 program 0 for normal operation. inverts pd polarity when 1. [5] r/w pd_up_en 1 1 enables the pd up output [6] r/w pd_dn_en 1 1 enables the pd dn output [8:7] r/w csp mode 2 0 cycle slip prevention mode extra current is driven into the loop flter when the phase error is larger than: 0: disabled 1: 5.4ns 2: 14.4ns 3: 24.1ns this delay varies by +- 10% with temperature, and +- 12% with process. [9] r/w force cp up 1 0 forces cp up output on - use for test only [10] r/w force cp dn 1 0 forces cp dn output on - use for test only [11] r/w force cp mid rail 1 0 force cp mid rail - use for test only [14:12] r/w reserved 3 0 program to 100 [16:15] r/w cp internal opamp bias 2 3 program to 11 [18:17] r/w mcounter clock gating 2 3 program 11 mcounter clock gating 0: mcounter off 1: n<128 2: n< 1023 3: all clocks on (recommended setting 11) [19] r/w spare 1 1 dont care [21:20] r/w reserved 2 0 program to 00 [23:22] r/w reserved 2 0 program to 00 2.14 reg 0ch exact frequency mode register (default 000000h ) bit type name width default description [13:0] r/w number of channels per fpd 14 0 comparison frequency divided by the correction rate, must be an integer. frequencies at exactly the correction rate will have zero frequency error. 0: disabled 1: disabled 2:16383d (3fffh) plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 56 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz 2.15 reg 0fh gpo_spi_rdiv register (default 000001 h) bit type name width default description [4:0] r/w gpo_select 5 1d signal selected here is output to sdo pin when enabled 0: data from reg0f[5] 1: lock detect output 2. lock detect trigger 3: lock detect window output 4: ring osc test 5. pullup hard from csp 6. pulldn hard from csp 7. reserved 8: reference buffer output 9: ref divider output 10: vco divider output 11. modulator clock from vco divider 12. auxiliary clock 13. aux spi clock 14. aux spi enable 15. aux spi data out 16. pd dn 17. pd up 18. sd3 clock delay 19. sd3 core clock 20. autostrobe integer write 21. autostrobe frac write 22. autostrobe aux spi 23. spi latch enable 24. vco divider sync reset 25. seed load strobe 26.-29 not used 30. spi output buffer en 31. soft rstb [5] r/w gpo test data 1 0 1 - gpo test data [6] r/w prevent automux sdo 1 0 1- outputs gpo data only 0 - automuxes between sdo and gpo data [7] r/w ldo driver always on 1 0 1- ld_sdo pin driver always on 0 - ld_sdo pin driver only on during spi read cycle [8] r/w disable pfet 1 0 program to 0 [9] r/w disable nfet 1 0 program to 0 plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 57 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz 2.16 reg 10h vco tune register (default 00002 0h) bit type name width default description [7:0] ro vco switch set ting 8 32d read only register. indicates the vco switch setting selected by the autocal state machine to yield the nearest free running vco frequency to the desired operating frequency. not valid when reg10h[8] = 1, autocal busy. note if a manual change is done to the vco switch settings this register will not indicate the current vco switch position. 0 = highest frequency 1 = 2nd highest ... 256 = lowest frequency note: vco subsystems may not use all the msbs, in which case the unused bits are dont care [8] ro autocal busy 1 0 busy when autocal state machine is searching for the nearest switch setting to the requested frequency. 2.17 reg 11h sar register (default 7ffffh) bit type name width default description [18:0] ro sar error mag counts 19 2 19 -1 sar error magnitude counts [19] ro sar error sign 1 0 sar error sign 0=+ve 1=-ve 2.18 reg 12h gpo2 register (default 000000h ) bit type name width default description [0] ro gpo 1 0 gpo state [1] ro lock detect 1 0 lock detect status 1 = locked 0 = unlocked 2.19 reg 13h bist register (default 1259h) bit type name width default description [15:0] ro bist signature 19 4697d bist signature [16] ro bist busy 1 0 bist busy plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 58 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz 3.0 vco subsystem register map please note th at th e vc o su bsystem us es in direct ad dressing vi a reg 05h . for more de tailed in formation on how to write to the vco subsystem please see section 1.19 vco serial port interface (spi) . 3.1 vco_reg 00h tuning bit type name width default description [0] wo cal 1 0 vco tune voltage is redirected to a temperature compensated ca libration vo ltage [8:1] wo caps 8 16d vco sub-band selection. 0 - max frequency 1111 1111 - min frequency. not all sub-bands are used on the various products. 3.2 vco_reg 01h enables bit type name width default description [0] wo master enable vco subsystem 1 1 0 - all vco subsystem blocks off manual mode ( vco_reg 03h [2] = 1) 1- anded with local enables only auto mode ( vco_reg 03h [2] = 0) 1- master enable ignores local enables [1] wo manual mode pll buffer enable 1 1 enables pll buffer in manual mode only [2] wo manual mode rf buffer enable 1 1 enables rf buffer to output in manual mode only [3] wo manual mode divide by 1 enable 1 1 enables rf divide by 1 in manual mode only [4] wo manual mode rf divider enable 1 1 enables rf divider in manual mode only [8:5] wo dont care 4 0 dont care for example, to tu rn dis able the rf bu ffer in the vc o su bsystem an d mu te the ou tput of the hm c833lp6ge, bi t 2 in vco_reg01h ne eds to be cl eared. if th e ot her bi ts ar e le ft un changed, th en 0 00 01 10 11 ne eds to be wr itten in to vco reg01h. th e vc o su bsystem re gister is ac cessed vi a a wr ite to pl l su bsystem reg 05h = 0 0001 10 11 00 01 000 = d88h reg 05h [2:0] = 000; vco subsystem id 0 reg 05h [6:3] = 0001; vco subsystem register address reg 05h [7] = 1; master enable reg 05h [8] = 1; pll buffer enable reg 05h [9] = 0; disable rf buffer reg 05h [10] = 1; divide by 1 enable reg 05h [11] = 1; rf divider enable reg 05h [16:12] = 0; dont care plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 59 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz 3.3 vco_reg 02h biases bit type name width default description [5:0] wo rf divide ratio 6 1 0 - mute, vco and pll buffer on, rf output stages off 1 - fo 2 - fo/2 3 - invalid, defaults to 2 4 - fo/4 5 - invalid, defaults to 4 6 - fo/6 ... 60 - fo/60 61 - invalid, defaults to 60 62 - fo/62 > 62 - invalid, defaults to 62 note: this register automatically controls the enables to the, rf output buffer, rf divider, rf divide by 1 path, and requires master enable ( vco_reg 01h [0] = 1) and autorfo mode ( vco_reg 03h [2] = 0) note: bit[0] is a dont care in manualrfo mode. [7:6] wo rf output buffer gain control 2 3 11 - max gain 10 - max gain - 3 db 01 - max gain - 6 db 00 - max gain - 9 db [8] wo divider output stage gain control 1 0 1 - max gain 0 - max gain - 3 db used to fatten the output power level across frequency ? for divide-by 1 or divide-by 2 it is recommended to set this bit to 1. 0 will reduce output power and degrade noise foor performance. ? for divide-by 4 or higher, it is recommended to set this bit to 0 to maintain fat output power across divider settings. setting this bit to 1, with divide-by 4 or higher provides higher output power compared to the divide- by 1 or 2 case. for example, to wr ite 0_ 1111_1110 in to vc o_reg02h vc o su bsystem (v co_id = 0 00b), an d se t th e vc o ou tput divider to divide by 62, the following needs to be written to reg 05h =0_1111_1110, 0010, 000 b. reg 05h [2:0] = 00; subsystem id 0 reg 05h [6:3] = 0010; vco register address 2d reg 05h [16:7] = 0 _1111_1110 ; divide by 62, max output rf gain, divider output stage gain = 0 3.4 vco_reg 03h confg bit type name width default description [0] wo fundamental/doubler mode selection 1 1 0- enable the frequency doubler mode of operation 1- enable fundamental mode of operation - for more information please see vco subsystem section. [1] wo reserved 1 0 reserved [2] wo manual rfo mode 1 0 0 - autorfo mode (recommended) 1 - manualrfo mode autorfo mode controls output buffers and rf divider enables according to rf divider setting in vco_reg 02h biases [5:0] manualrfo mode requires manual enables of individual blocks via vco_reg01h [4:3] wo rf buffer bias 2 2 program to 10b for output frequencies <=3000mhz (when vco_reg 03h [0]=1). program to 00b for output frequencies >3000mhz (when vco_reg 03h [0]=0) plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 60 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz 3.4 vco_reg 03h confg bit type name width default description [8:5] wo spare 4 2 dont care 3.5 vco_reg 04h cal/bias specifed p erformance i s o nly g uaranteed w ith t he r equired s ettings i n t his t able. o ther s ettings a re n ot supported. bit type name width default description [2:0] wo vco bias 3 1 program to 1d [4:3] wo pll buffer bias 2 1 program to 0d [6:5] wo fndlmtr bias 2 2 program to 2d [8:7] wo preset cal 0 2 1 program to 1d 3.6 vco_reg05h cf_cal bit type name width default description [1:0] wo cf l 2 2 program to 0d [3:2] wo cf ml 2 2 program to 3d [5:4] wo cf mh 2 2 program to 2d [7:6] wo cf h 2 2 program to 0d [8] wo spare 1 0 program to 0d 3.7 vco_reg06h msb cal bit type name width default description [1:0] wo msb l 2 3 program to 3d [3:2] wo msb ml 2 3 program to 3d [5:4] wo msb mh 2 3 program to 3d [7:6] wo msb h 2 3 program to 3d [8] wo spare 1 0 dont care plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
7 - 61 HMC833LP6GE v03.714 fractional-n pll with integrated vco 25 - 6000 mhz notes: plls with integrated vco - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d

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